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Searched refs:OP1 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16-v4-instructions.ll7 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
32 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
48 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
64 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
182 ; CHECK-COMMON-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
183 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP1]]
192 ; CHECK-COMMON-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
219 ; CHECK-CVT-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
229 ; CHECK-COMMON-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsubtract-of-one-hand-of-select.ll15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[FALSEVAL:%.*]], [[OP1:%.*]]
25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[TRUEVAL:%.*]], [[OP1:%.*]]
38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[FALSEVAL:%.*]], [[OP1:%.*]]
53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP1:%.*]], i8 [[FALSEVAL:%.*]]
55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[O]], [[OP1]]
69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[O]], [[OP1:%.*]]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfusion-elementwise-options.mlir59 // CHECK: %[[OP1:.+]] = linalg.generic {{.+}} ins(%[[ARG2]], %[[ARG3]]
61 // CHECK: %[[OP3:.+]] = linalg.generic {{.+}} ins(%[[ARG0]], %[[ARG1]], %[[OP1]], %[[OP2]]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp261 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
265 SDNode *OP1N = OP1.getNode(); in PreprocessLoad()
281 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
283 dyn_cast<GlobalAddressSDNode>(OP1.getNode())) in PreprocessLoad()
/llvm-project-15.0.7/mlir/test/mlir-pdll/CodeGen/MLIR/
H A Dexpr.pdll47 // CHECK: %[[OP1:.*]] = operation
48 // CHECK: %[[OP1_RES:.*]] = results of %[[OP1]]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]]
7 ; CHECK: lsr([[OP1]],#{{[0-9]+}})
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Defines.h38 OP1 = (1 << 10), enumerator
H A DR600InstrInfo.cpp121 return ((TargetFlags & R600_InstFlag::OP1) | in hasInstrModifiers()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp134 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
/llvm-project-15.0.7/mlir/test/Conversion/PDLToPDLInterp/
H A Dpdl-to-pdl-interp-matcher.mlir423 // CHECK-DAG: %[[OP1:.*]] = pdl_interp.get_defining_op of %[[VAL1]]
431 // CHECK-DAG: pdl_interp.is_not_null %[[OP1]] : !pdl.operation -> ^{{.*}}, ^[[CONTINUE]]
/llvm-project-15.0.7/flang/test/Fir/
H A Dconvert-to-llvm.fir1129 // CHECK-SAME: ([[OP1:%.*]]: i64) -> !llvm.ptr<array<32 x array<16 x array<8 x f32>
1132 // CHECK: [[MUL1:%.*]] = llvm.mul [[ONE]], [[OP1]] : i64
1148 // CHECK-SAME: ([[OP1:%.*]]: i64) -> !llvm.ptr<array<9 x array<8 x f32>
1151 // CHECK: [[MUL1:%.*]] = llvm.mul [[ONE]], [[OP1]] : i64
/llvm-project-15.0.7/llvm/lib/Target/
H A DREADME.txt2143 errs() << "OP1 = " << *Op1 << " U=" << Op1->getNumUses() << "\n";