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Searched refs:NumMicroOps (Results 1 – 25 of 71) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td65 let NumMicroOps = 2;
71 let NumMicroOps = 2;
76 let NumMicroOps = 2;
81 let NumMicroOps = 2;
85 let NumMicroOps = 2;
89 let NumMicroOps = 2;
93 let NumMicroOps = 2;
97 let NumMicroOps = 2;
101 let NumMicroOps = 2;
105 let NumMicroOps = 2;
[all …]
H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
78 let Latency = 2; let NumMicroOps = 2;
84 let Latency = 2; let NumMicroOps = 2;
90 let Latency = 2; let NumMicroOps = 2;
96 let Latency = 3; let NumMicroOps = 4;
102 let Latency = 5; let NumMicroOps = 4;
[all …]
H A DAArch64SchedAmpere1.td59 let NumMicroOps = 1;
64 let NumMicroOps = 2;
69 let NumMicroOps = 1;
74 let NumMicroOps = 1;
79 let NumMicroOps = 1;
84 let NumMicroOps = 1;
89 let NumMicroOps = 2;
94 let NumMicroOps = 1;
99 let NumMicroOps = 2;
104 let NumMicroOps = 2;
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H A DAArch64SchedThunderX3T110.td121 let NumMicroOps = 2;
127 let NumMicroOps = 2;
133 let NumMicroOps = 2;
139 let NumMicroOps = 3;
146 let NumMicroOps = 4;
153 let NumMicroOps = 4;
159 let NumMicroOps = 2;
165 let NumMicroOps = 3;
171 let NumMicroOps = 2;
177 let NumMicroOps = 3;
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H A DAArch64SchedFalkorDetails.td36 let NumMicroOps = 0;
40 let NumMicroOps = 0;
44 let NumMicroOps = 0;
48 let NumMicroOps = 0;
94 let NumMicroOps = 2;
98 let NumMicroOps = 2;
102 let NumMicroOps = 2;
106 let NumMicroOps = 2;
110 let NumMicroOps = 2;
114 let NumMicroOps = 2;
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H A DAArch64SchedExynosM5.td138 let NumMicroOps = 0; }
140 let NumMicroOps = 0; }
211 let NumMicroOps = 1; }
214 let NumMicroOps = 2; }
218 let NumMicroOps = 2; }
221 let NumMicroOps = 2; }
224 let NumMicroOps = 2; }
230 let NumMicroOps = 6;
237 let NumMicroOps = 6;
241 let NumMicroOps = 1;
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H A DAArch64SchedExynosM3.td112 let NumMicroOps = 1; }
114 let NumMicroOps = 0; }
121 let NumMicroOps = 2; }
155 let NumMicroOps = 1; }
158 let NumMicroOps = 2; }
162 let NumMicroOps = 2; }
165 let NumMicroOps = 2; }
168 let NumMicroOps = 2; }
170 let NumMicroOps = 0; }
228 let NumMicroOps = 0; }
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H A DAArch64SchedThunderX2T99.td98 let NumMicroOps = 2;
104 let NumMicroOps = 2;
110 let NumMicroOps = 2;
117 let NumMicroOps = 4;
124 let NumMicroOps = 4;
130 let NumMicroOps = 2;
136 let NumMicroOps = 2;
142 let NumMicroOps = 3;
148 let NumMicroOps = 3;
154 let NumMicroOps = 2;
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H A DAArch64SchedExynosM4.td138 let NumMicroOps = 0; }
140 let NumMicroOps = 0; }
148 let NumMicroOps = 2; }
152 let NumMicroOps = 3; }
192 let NumMicroOps = 1; }
195 let NumMicroOps = 2; }
199 let NumMicroOps = 2; }
202 let NumMicroOps = 2; }
205 let NumMicroOps = 2; }
207 let NumMicroOps = 0; }
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H A DAArch64SchedKryo.td69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
73 { let Latency = 2; let NumMicroOps = 2; }
76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
78 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
90 { let Latency = 3; let NumMicroOps = 2; }
96 { let Latency = 6; let NumMicroOps = 2; }
98 { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
H A DAArch64SchedNeoverseN2.td124 let NumMicroOps = 2;
129 let NumMicroOps = 2;
134 let NumMicroOps = 2;
139 let NumMicroOps = 2;
144 let NumMicroOps = 2;
149 let NumMicroOps = 2;
154 let NumMicroOps = 2;
159 let NumMicroOps = 2;
164 let NumMicroOps = 2;
169 let NumMicroOps = 2;
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td91 let NumMicroOps = 2;
97 let NumMicroOps = 2;
102 let NumMicroOps = 2;
107 let NumMicroOps = 2;
112 let NumMicroOps = 2;
117 let NumMicroOps = 2;
121 let NumMicroOps = 2;
125 let NumMicroOps = 2;
129 let NumMicroOps = 2;
133 let NumMicroOps = 2;
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td170 let NumMicroOps = 3;
427 let NumMicroOps = 2;
432 let NumMicroOps = 2;
438 let NumMicroOps = 2;
442 let NumMicroOps = 3;
492 let NumMicroOps = 3;
497 let NumMicroOps = 4;
504 let NumMicroOps = 9;
516 let NumMicroOps = 3;
521 let NumMicroOps = 4;
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H A DX86SchedHaswell.td189 let NumMicroOps = 3;
487 let NumMicroOps = 2;
492 let NumMicroOps = 2;
498 let NumMicroOps = 2;
502 let NumMicroOps = 3;
510 let NumMicroOps = 3;
515 let NumMicroOps = 4;
522 let NumMicroOps = 9;
534 let NumMicroOps = 3;
539 let NumMicroOps = 4;
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H A DX86SchedBroadwell.td187 let NumMicroOps = 3;
488 let NumMicroOps = 2;
493 let NumMicroOps = 2;
498 let NumMicroOps = 2;
502 let NumMicroOps = 3;
510 let NumMicroOps = 3;
515 let NumMicroOps = 4;
522 let NumMicroOps = 9;
534 let NumMicroOps = 3;
539 let NumMicroOps = 4;
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H A DX86SchedSkylakeServer.td171 let NumMicroOps = 3;
428 let NumMicroOps = 2;
433 let NumMicroOps = 2;
439 let NumMicroOps = 2;
443 let NumMicroOps = 3;
493 let NumMicroOps = 3;
498 let NumMicroOps = 4;
505 let NumMicroOps = 9;
517 let NumMicroOps = 3;
522 let NumMicroOps = 4;
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H A DX86SchedIceLake.td179 let NumMicroOps = 3;
436 let NumMicroOps = 2;
441 let NumMicroOps = 2;
447 let NumMicroOps = 2;
451 let NumMicroOps = 3;
501 let NumMicroOps = 3;
506 let NumMicroOps = 4;
513 let NumMicroOps = 9;
525 let NumMicroOps = 3;
530 let NumMicroOps = 4;
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H A DX86SchedSandyBridge.td182 let NumMicroOps = 3;
454 let NumMicroOps = 2;
458 let NumMicroOps = 2;
463 let NumMicroOps = 2;
467 let NumMicroOps = 3;
489 let NumMicroOps = 3;
494 let NumMicroOps = 4;
511 let NumMicroOps = 3;
516 let NumMicroOps = 4;
539 let NumMicroOps = 2;
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H A DX86ScheduleBdVer2.td330 let NumMicroOps = 1;
337 let NumMicroOps = 4;
344 let NumMicroOps = 2;
356 let NumMicroOps = 2;
381 let NumMicroOps = 3;
388 let NumMicroOps = 5;
395 let NumMicroOps = 6;
417 let NumMicroOps = 2;
424 let NumMicroOps = 4;
460 let NumMicroOps = 5;
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H A DX86ScheduleZnver3.td647 let NumMicroOps = !add(Zn3WriteCMPXCHG8rr.NumMicroOps, 2);
758 let NumMicroOps = !add(Zn3WriteRotateR1.NumMicroOps, 1);
773 let NumMicroOps = !add(Zn3WriteRotateRightRI.NumMicroOps, 3);
787 let NumMicroOps = !add(Zn3WriteRotateLeftRI.NumMicroOps, 2);
817 let NumMicroOps = !add(Zn3WriteRotateLeftRCL.NumMicroOps, 2);
1230 let NumMicroOps = !add(Zn3WriteSHA1MSG1rr.NumMicroOps, 0);
1258 let NumMicroOps = !add(Zn3WriteSHA256MSG1rr.NumMicroOps, 0);
1272 let NumMicroOps = !add(Zn3WriteSHA256MSG2rr.NumMicroOps, 1);
1361 let NumMicroOps = !add(Zn3WriteVPERMPSYrr.NumMicroOps, 1);
1375 let NumMicroOps = !add(Zn3WriteVPERMYri.NumMicroOps, 1);
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H A DX86ScheduleZnver1.td249 let NumMicroOps = 0;
253 let NumMicroOps = ZnWriteIMulH.NumMicroOps;
459 let NumMicroOps = 2;
469 let NumMicroOps = 2;
537 let NumMicroOps = 2;
547 let NumMicroOps = 2;
639 let NumMicroOps = 2;
648 let NumMicroOps = 2;
685 let NumMicroOps = 2;
710 let NumMicroOps = 2;
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H A DX86ScheduleZnver2.td248 let NumMicroOps = 0;
252 let NumMicroOps = Zn2WriteIMulH.NumMicroOps;
454 let NumMicroOps = 2;
464 let NumMicroOps = 2;
531 let NumMicroOps = 2;
539 let NumMicroOps = 2;
549 let NumMicroOps = 2;
645 let NumMicroOps = 2;
654 let NumMicroOps = 2;
691 let NumMicroOps = 2;
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/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp63 const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps(); in checkRCU() local
64 if (RCU.isAvailable(NumMicroOps)) in checkRCU()
81 const unsigned NumMicroOps = IS.getNumMicroOps(); in dispatch() local
82 if (NumMicroOps > DispatchWidth) { in dispatch()
85 CarryOver = NumMicroOps - DispatchWidth; in dispatch()
88 assert(AvailableEntries >= NumMicroOps); in dispatch()
89 AvailableEntries -= NumMicroOps; in dispatch()
130 std::min(DispatchWidth, NumMicroOps)); in dispatch()
160 unsigned NumMicroOps = Inst.getNumMicroOps(); in isAvailable() local
161 unsigned Required = std::min(NumMicroOps, DispatchWidth); in isAvailable()
H A DInOrderIssueStage.cpp65 unsigned NumMicroOps = Inst.getNumMicroOps(); in isAvailable() local
67 bool ShouldCarryOver = NumMicroOps > getIssueWidth(); in isAvailable()
68 if (Bandwidth < NumMicroOps && !ShouldCarryOver) in isAvailable()
230 unsigned NumMicroOps = IS.getNumMicroOps(); in tryIssue() local
231 notifyInstructionDispatched(IR, NumMicroOps, UsedRegs); in tryIssue()
247 bool ShouldCarryOver = NumMicroOps > Bandwidth; in tryIssue()
249 CarryOver = NumMicroOps - Bandwidth; in tryIssue()
255 NumIssued += NumMicroOps; in tryIssue()
256 Bandwidth = IS.getEndGroup() ? 0 : Bandwidth - NumMicroOps; in tryIssue()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp28 LastInstructionIdx(0), TotalCycles(0), NumMicroOps(0), in SummaryView()
55 NumMicroOps += Desc.NumMicroOps; in onEvent()
92 DV.TotalUOps = NumMicroOps * DV.Iterations; in collectData()
95 DV.BlockRThroughput = computeBlockRThroughput(SM, DispatchWidth, NumMicroOps, in collectData()

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