Searched refs:NextVT (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3959 EVT NextVT; in CollectOpsToWiden() local
3962 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); in CollectOpsToWiden()
3963 } while (!TLI.isTypeLegal(NextVT)); in CollectOpsToWiden()
3967 SDValue VecOp = DAG.getUNDEF(NextVT); in CollectOpsToWiden()
3970 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
3988 NextVT, SubConcatOps); in CollectOpsToWiden()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28747 MVT NextVT = MVT::getVectorVT(NextSVT, CurrNumElts / 2); in LowerVectorCTLZInRegLUT() local
28748 SDValue Shift = DAG.getConstant(CurrScalarSizeInBits, DL, NextVT); in LowerVectorCTLZInRegLUT()
28760 HiZ = DAG.getBitcast(NextVT, HiZ); in LowerVectorCTLZInRegLUT()
28765 SDValue ResNext = Res = DAG.getBitcast(NextVT, Res); in LowerVectorCTLZInRegLUT()
28766 SDValue R0 = DAG.getNode(ISD::SRL, DL, NextVT, ResNext, Shift); in LowerVectorCTLZInRegLUT()
28767 SDValue R1 = DAG.getNode(ISD::SRL, DL, NextVT, HiZ, Shift); in LowerVectorCTLZInRegLUT()
28768 R1 = DAG.getNode(ISD::AND, DL, NextVT, ResNext, R1); in LowerVectorCTLZInRegLUT()
28769 Res = DAG.getNode(ISD::ADD, DL, NextVT, R0, R1); in LowerVectorCTLZInRegLUT()
28770 CurrVT = NextVT; in LowerVectorCTLZInRegLUT()
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