| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 145 CCValAssign NextVA = VAs[1]; in assignCustomValue() local
147 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); in assignCustomValue()
149 assert(VA.getValNo() == NextVA.getValNo() && in assignCustomValue()
153 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
166 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
171 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
320 CCValAssign NextVA = VAs[1]; in assignCustomValue() local
322 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); in assignCustomValue()
324 assert(VA.getValNo() == NextVA.getValNo() && in assignCustomValue()
328 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
[all …]
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| H A D | ARMISelLowering.h | 777 CCValAssign &VA, CCValAssign &NextVA,
782 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| H A D | ARMFastISel.cpp | 1989 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs() local
1991 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
1996 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1999 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
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| H A D | ARMISelLowering.cpp | 2285 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
2295 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
2296 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
2298 assert(NextVA.isMemLoc()); in PassF64ArgInRegs()
2306 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff); in PassF64ArgInRegs()
4277 CCValAssign &NextVA, in GetF64FormalArgument() argument
4295 if (NextVA.isMemLoc()) { in GetF64FormalArgument()
4297 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true); in GetF64FormalArgument()
4305 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
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| /llvm-project-15.0.7/clang/include/clang/AST/ |
| H A D | StmtIterator.h | 71 void NextVA();
97 NextVA();
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| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | StmtIterator.cpp | 37 void StmtIteratorBase::NextVA() { in NextVA() function in StmtIteratorBase
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 470 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments_32() local
473 if (NextVA.isMemLoc()) { in LowerFormalArguments_32()
475 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); in LowerFormalArguments_32()
479 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
952 CCValAssign &NextVA = ArgLocs[++i]; in LowerCall_32() local
953 if (NextVA.isRegLoc()) { in LowerCall_32()
954 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1)); in LowerCall_32()
957 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; in LowerCall_32()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3704 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments() local
3706 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3060 CCValAssign &NextVA, const X86Subtarget &Subtarget) { in Passv64i1ArgInRegs() argument
3064 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
3079 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi)); in Passv64i1ArgInRegs()
3349 static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, in getv64i1Argument() argument
3357 assert(NextVA.getValVT() == VA.getValVT() && in getv64i1Argument()
3359 assert(VA.isRegLoc() && NextVA.isRegLoc() && in getv64i1Argument()
3374 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in getv64i1Argument()
3383 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag); in getv64i1Argument()
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