| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineSSAUpdater.cpp | 124 Register NewVR = MRI->createVirtualRegister(RC); in InsertNewDef() local
125 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR); in InsertNewDef()
236 Register NewVR; in RewriteUse() local
239 NewVR = GetValueAtEndOfBlockInternal(SourceBB); in RewriteUse()
241 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
244 U.setReg(NewVR); in RewriteUse()
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| H A D | PeepholeOptimizer.cpp | 605 Register NewVR = MRI->createVirtualRegister(RC); in INITIALIZE_PASS_DEPENDENCY() local
607 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
612 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
785 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI() local
788 TII.get(TargetOpcode::PHI), NewVR); in insertPHI()
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| H A D | TargetInstrInfo.cpp | 862 Register NewVR = MRI.createVirtualRegister(RC); in reassociateOps() local
863 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in reassociateOps()
872 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR) in reassociateOps()
879 .addReg(NewVR, getKillRegState(true)) in reassociateOps()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5573 Register NewVR = MRI.createVirtualRegister(RC); in genNeg() local
5580 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in genNeg()
5582 return NewVR; in genNeg()
5594 Register NewVR = in genFusedMultiplyAccNeg() local
5621 Register NewVR = in genFusedMultiplyIdxNeg() local
5718 .addReg(NewVR, getKillRegState(true)) in genSubAdd2SubSub()
6407 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
6454 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
6514 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
6534 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
[all …]
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| H A D | AArch64ISelLowering.cpp | 20747 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
20757 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
20764 .addReg(NewVR); in insertCopiesSplitCSR()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 1385 Register NewVR = MRI->createVirtualRegister(RC); in generateInserts() local
1386 RegMap[VR] = NewVR; in generateInserts()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 8482 Register NewVR = in enforceOperandRCAlignment() local
8485 BuildMI(*BB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewVR) in enforceOperandRCAlignment()
8490 Op.setReg(NewVR); in enforceOperandRCAlignment()
8492 MI.addOperand(MachineOperand::CreateReg(NewVR, false, true)); in enforceOperandRCAlignment()
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| H A D | SIISelLowering.cpp | 2325 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
2328 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
2335 .addReg(NewVR); in insertCopiesSplitCSR()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 21756 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
21766 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
21773 .addReg(NewVR); in insertCopiesSplitCSR()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 56425 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
56435 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
56442 .addReg(NewVR); in insertCopiesSplitCSR()
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