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Searched refs:NewDestReg (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp290 Register NewDestReg; in tryReplaceLoad() local
296 if (!getSuperRegDestIfDead(MI, NewDestReg)) in tryReplaceLoad()
301 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg); in tryReplaceLoad()
325 Register NewDestReg; in tryReplaceCopy() local
326 if (!getSuperRegDestIfDead(MI, NewDestReg)) in tryReplaceCopy()
335 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
344 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg) in tryReplaceCopy()
350 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
358 Register NewDestReg; in tryReplaceExtend() local
359 if (!getSuperRegDestIfDead(MI, NewDestReg)) in tryReplaceExtend()
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H A DX86RegisterInfo.cpp765 Register NewDestReg = MI.getOperand(0).getReg(); in tryOptimizeLEAtoMOV() local
768 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr, in tryOptimizeLEAtoMOV()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp98 Register NewDestReg = MI.getOperand(0).getReg(); in convertToFlagSetting() local
100 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
103 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp591 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV() local
594 DbgLoc, TII.get(Opc), NewDestReg) in ARMMaterializeGV()
598 return NewDestReg; in ARMMaterializeGV()
606 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV() local
609 TII.get(ARM::t2LDRi12), NewDestReg) in ARMMaterializeGV()
614 TII.get(ARM::LDRi12), NewDestReg) in ARMMaterializeGV()
617 DestReg = NewDestReg; in ARMMaterializeGV()
2993 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF() local
2995 TII.get(ARM::t2LDRi12), NewDestReg) in ARMLowerPICELF()
2998 DestReg = NewDestReg; in ARMLowerPICELF()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp66 void replaceDef(unsigned OldDestReg, unsigned NewDestReg);
206 void PHILinearize::replaceDef(unsigned OldDestReg, unsigned NewDestReg) { in replaceDef() argument
207 phiInfoElementSetDef(findPHIInfoElement(OldDestReg), NewDestReg); in replaceDef()
2403 Register NewDestReg = MRI->createVirtualRegister(RegClass); in splitLoopPHI() local
2404 LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI); in splitLoopPHI()
2407 TII->get(TargetOpcode::PHI), NewDestReg); in splitLoopPHI()
2408 LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI) in splitLoopPHI()
H A DSIInstrInfo.cpp876 MCRegister NewDestReg = RI.get32BitRegister(DestReg); in copyPhysReg() local
885 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg) in copyPhysReg()
896 copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc); in copyPhysReg()
906 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg) in copyPhysReg()
911 auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg) in copyPhysReg()
920 .addReg(NewDestReg, RegState::Implicit | RegState::Undef); in copyPhysReg()