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Searched refs:Neon (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-sve-asm-negative.ll5 ; constraint be used with a Neon register.
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DARMTargetParser.def36 ARM_FPU("neon", FK_NEON, FPUVersion::VFPV3, NeonSupportLevel::Neon, FPURestriction::None)
37 ARM_FPU("neon-fp16", FK_NEON_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::Neon, FPURestriction::…
38 ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FPUVersion::VFPV4, NeonSupportLevel::Neon, FPURestriction::Non…
39 ARM_FPU("neon-fp-armv8", FK_NEON_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::Neon, FPURestrictio…
H A DARMTargetParser.h157 Neon, ///< Neon enumerator
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dmem-op-cost-model.ll1 ; Check memory cost model action for fixed vector SVE and Neon
2 ; Vector bits size lower than 256 bits end up assuming Neon cost model
/llvm-project-15.0.7/llvm/lib/Support/
H A DARMTargetParser.cpp232 {"+neon", "-neon", NeonSupportLevel::Neon}, in getFPUFeatures()
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/AArch64/
H A DMachO_arm64_relocations.s79 # variants and all LDR/Neon variants.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3312 // Neon 2-register comparisons.
3372 // Neon 3-register comparisons.
3426 // Neon 2-register vector intrinsics,
3498 // Neon 3-register vector operations.
3553 // Neon 3-register vector intrinsics.
3801 // Neon Multiply-Op vector operations,
3840 // Neon Intrinsic-Op vector operations,
3863 // Neon 3-argument intrinsics,
3920 // Neon Long 3-argument intrinsics.
4204 // Neon Shift Long operations,
[all …]
H A DARMInstrFormats.td133 def NeonDomain : Domain<2>; // Instructions in Neon domain only
134 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
135 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
H A DARMScheduleR52.td539 // Neon Support
H A DARM.td36 // Floating Point, HW Division and Neon Support
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td56 // Port 6: FP/Neon/SIMD/Crypto.
59 // Port 7: FP/Neon/SIMD/Crypto.
62 // Port 8: FP/Neon/SIMD/Crypto.
65 // Port 9: FP/Neon/SIMD/Crypto.
H A DAArch64RegisterInfo.td768 // The part of SVE registers that don't overlap Neon registers.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Daes-erratum-fix.ll12 ; instruction in a fused aes pair was set by 64-bit Neon register writes or
13 ; 128-bit Neon register writes. All other register writes are unsafe, and
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DDiagnosticSemaKinds.td3024 "Neon vector size must be 64 or 128 bits">;