Searched refs:NegDivScale0 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3934 auto NegDivScale0 = B.buildFNeg(S32, DenominatorScaled, Flags); in legalizeFDIV32() local
3941 auto Fma0 = B.buildFMA(S32, NegDivScale0, ApproxRcp, One, Flags); in legalizeFDIV32()
3944 auto Fma2 = B.buildFMA(S32, NegDivScale0, Mul, NumeratorScaled, Flags); in legalizeFDIV32()
3946 auto Fma4 = B.buildFMA(S32, NegDivScale0, Fma3, NumeratorScaled, Flags); in legalizeFDIV32()
3991 auto NegDivScale0 = B.buildFNeg(S64, DivScale0.getReg(0), Flags); in legalizeFDIV64() local
3997 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); in legalizeFDIV64()
3999 auto Fma2 = B.buildFMA(S64, NegDivScale0, Fma1, One, Flags); in legalizeFDIV64()
4009 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64()
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| H A D | SIISelLowering.cpp | 9013 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32() local
9046 NegDivScale0, in LowerFDIV32()
9051 NegDivScale0 = DAG.getMergeValues(Ops, SL); in LowerFDIV32()
9054 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
9055 ApproxRcp, One, NegDivScale0, Flags); in LowerFDIV32()
9063 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
9069 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, in LowerFDIV32()
9116 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64() local
9120 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
9124 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
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