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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Drotr.ll58 ; GCN: v_sub_nc_u16_e64 [[NX:v[0-9]+]], 0, [[X]]
60 ; GCN: v_and_b32_e32 [[NXAND:v[0-9]+]], 15, [[NX]]
H A Drotl.ll62 ; GCN: v_sub_nc_u16_e64 [[NX:v[0-9]+]], 0, [[X]]
64 ; GCN: v_and_b32_e32 [[NXAND:v[0-9]+]], 15, [[NX]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dvec_shuffle.ll1829 ; CHECK-NEXT: [[NX:%.*]] = fneg nsz <2 x float> [[X:%.*]]
1830 ; CHECK-NEXT: call void @use(<2 x float> [[NX]])
1858 ; CHECK-NEXT: [[NX:%.*]] = fneg nnan <2 x float> [[X:%.*]]
1859 ; CHECK-NEXT: call void @use(<2 x float> [[NX]])
1892 ; CHECK-NEXT: [[NX:%.*]] = fneg nnan <2 x float> [[X:%.*]]
1893 ; CHECK-NEXT: call void @use(<2 x float> [[NX]])
1931 ; CHECK-NEXT: [[NX:%.*]] = sitofp <2 x i32> [[X:%.*]] to <2 x half>
1953 ; CHECK-NEXT: [[NX:%.*]] = fptosi <2 x half> [[X:%.*]] to <2 x i16>
1964 ; CHECK-NEXT: [[NX:%.*]] = fptoui <2 x half> [[X:%.*]] to <2 x i32>
2110 ; CHECK-NEXT: call void @use4(<4 x float> [[NX]])
[all …]
H A Dminmax-intrinsics.ll1117 ; CHECK-NEXT: call void @use(i8 [[NX]])
1149 ; CHECK-NEXT: call void @use(i8 [[NX]])
1213 ; CHECK-NEXT: call void @use(i8 [[NX]])
1236 ; CHECK-NEXT: call void @use(i8 [[NX]])
1261 ; CHECK-NEXT: call void @use(i8 [[NX]])
1285 ; CHECK-NEXT: call void @use(i8 [[NX]])
1312 ; CHECK-NEXT: call void @use(i8 [[NX]])
1339 ; CHECK-NEXT: call void @use(i8 [[NX]])
1369 ; CHECK-NEXT: call void @use(i8 [[NX]])
1399 ; CHECK-NEXT: call void @use(i8 [[NX]])
[all …]
H A Dmax-of-nots.ll46 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
49 ; CHECK-NEXT: call void @extra_use(i8 [[NX]])
62 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
64 ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[NX]], i8 [[NY]])
65 ; CHECK-NEXT: call void @extra_use(i8 [[NX]])
103 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
108 ; CHECK-NEXT: call void @extra_use(i8 [[NX]])
H A Dxor.ll588 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
589 ; CHECK-NEXT: store i8 [[NX]], i8* [[P:%.*]], align 1
605 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
606 ; CHECK-NEXT: [[OR:%.*]] = or i8 [[NX]], 7
624 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
625 ; CHECK-NEXT: store i8 [[NX]], i8* [[P:%.*]], align 1
641 ; CHECK-NEXT: [[NX:%.*]] = and i8 [[X:%.*]], 42
642 ; CHECK-NEXT: [[AND:%.*]] = xor i8 [[NX]], 42
644 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[NX]], 53
H A Dfmul.ll214 ; CHECK-NEXT: [[NX:%.*]] = fneg float [[X:%.*]]
217 ; CHECK-NEXT: call void @use_f32(float [[NX]])
231 ; CHECK-NEXT: [[NX:%.*]] = fneg float [[X:%.*]]
234 ; CHECK-NEXT: call void @use_f32(float [[NX]])
248 ; CHECK-NEXT: [[NX:%.*]] = fneg float [[X:%.*]]
251 ; CHECK-NEXT: call void @use_f32(float [[NX]])
265 ; CHECK-NEXT: [[NX:%.*]] = fneg float [[X:%.*]]
268 ; CHECK-NEXT: call void @use_f32(float [[NX]])
H A Dfneg.ll770 ; CHECK-NEXT: [[NX:%.*]] = fneg ninf float [[X:%.*]]
771 ; CHECK-NEXT: call void @use(float [[NX]])
801 ; CHECK-NEXT: [[NX:%.*]] = fneg float [[X:%.*]]
802 ; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], float [[NX]], float [[Y:%.*]]
H A Dsub-minmax.ll499 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X]], -1
500 ; CHECK-NEXT: call void @use8(i8 [[NX]])
503 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[NX]], i8 [[NY]])
505 ; CHECK-NEXT: [[SUBX:%.*]] = sub i8 [[NX]], [[M]]
H A Dsub.ll182 ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
185 ; CHECK-NEXT: call void @use8(i8 [[NX]])
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Dmangle.mm46 @interface NX interface
50 @implementation NX implementation
/llvm-project-15.0.7/mlir/test/Conversion/TosaToLinalg/
H A Dtosa-to-linalg-named.mlir226 // CHECK: [[NX:%.+]] = arith.subi [[WIDTH]], [[IDX2]]
247 // CHECK: [[SUBP3:%.+]] = arith.subi [[NX]], [[PAD3]]
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaTemplateDeduction.cpp198 if (NamedDecl *NX = dyn_cast<NamedDecl>(X)) in isSameDeclaration() local
199 X = NX->getUnderlyingDecl(); in isSameDeclaration()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ16.td474 def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
H A DSystemZScheduleZ15.td474 def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6421 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X); in LowerCTTZ() local
6422 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX); in LowerCTTZ()