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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.image.nsa.ll2 …=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX1010-NSA %s
3 …=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX1030-NSA %s
5 …ch=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX11-NSA %s
9 ; TODO: use NSA here
22 ; NSA: image_sample v[0:3], [v1, v2, v0],
75 ; GFX1010-NSA: image_sample v9, v[5:7],
77 ; GFX1030-NSA: image_sample v1, v[5:7],
79 ; GFX11-NSA: image_sample v1, v[5:7],
91 ; GFX1010-NSA: image_sample v9, v[5:7],
93 ; GFX1030-NSA: image_sample v1, v[5:7],
[all …]
H A Dsgpr-regalloc-flags.ll24 ; DEFAULT-NEXT: GCN NSA Reassign
52 ; BASIC-DEFAULT-NEXT: GCN NSA Reassign
64 ; DEFAULT-BASIC-NEXT: GCN NSA Reassign
82 ; BASIC-BASIC-NEXT: GCN NSA Reassign
H A Dnsa-vmem-hazard.mir39 # Non-NSA
H A Dllc-pipeline.ll346 ; GCN-O1-NEXT: GCN NSA Reassign
636 ; GCN-O1-OPTS-NEXT: GCN NSA Reassign
928 ; GCN-O2-NEXT: GCN NSA Reassign
1233 ; GCN-O3-NEXT: GCN NSA Reassign
H A Dllvm.amdgcn.intersect_ray.ll161 ; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx1013_vaddr_cdc744.rst15 … using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
H A Dgfx1030_vaddr_cdc744.rst15 … using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
H A Dgfx10_vaddr_cdc744.rst15 … using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
H A Dgfx1013_vaddr_49d53a.rst15 … using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
H A Dgfx1030_vaddr_49d53a.rst15 … using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp179 bool NSA = false; in CheckNSA() local
232 NSA = true; in CheckNSA()
235 return NSA ? NSA_Status::NON_CONTIGUOUS : NSA_Status::CONTIGUOUS; in CheckNSA()
H A DMIMGInstructions.td15 // - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding
16 // - MIMGEncGfx10NSA: gfx10 NSA encoding
17 // - MIMGEncGfx11Default: gfx11 default (non-NSA) encoding
18 // - MIMGEncGfx11NSA: gfx11 NSA encoding
248 int NSA = !if(!le(num_addrs, 1), ?,
277 // Base class of all non-NSA gfx10 MIMG instructions.
290 // Base class for all NSA MIMG instructions.
305 let nsa = nsah.NSA;
308 // Base class of all non-NSA gfx11 MIMG instructions.
321 // Base class for all NSA MIMG instructions.
[all …]
H A DAMDGPU.td237 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
243 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
488 "Support NSA encoding for image instructions"
/llvm-project-15.0.7/clang/test/CXX/drs/
H A Ddr1xx.cpp414 namespace NSA { namespace
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUOperandSyntax.rst85 GFX10 *Image* instructions may use special *NSA* (Non-Sequential Address) syntax for *image address…
95 in *NSA* sequence are not required to have
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx10_mimg.txt309 # MIMG, NSA address
312 # NOTE: Contents of unused NSA bytes are NOT preserved.