Searched refs:MulRHS (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1227 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1); in emitAddSub() local
1231 std::swap(MulLHS, MulRHS); in emitAddSub()
1233 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt."); in emitAddSub()
1234 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub()
1596 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1); in emitLogicalOp() local
1600 std::swap(MulLHS, MulRHS); in emitLogicalOp()
1602 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt."); in emitLogicalOp()
1603 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 751 if (const SCEVMulExpr *MulRHS = dyn_cast<SCEVMulExpr>(RHS)) { in getExactSDiv() local
752 if (IgnoreSignificantBits || isMulSExtable(MulRHS, SE)) { in getExactSDiv()
755 dyn_cast<SCEVConstant>(MulRHS->getOperand(0)); in getExactSDiv()
758 SmallVector<const SCEV *, 4> ROps(drop_begin(MulRHS->operands())); in getExactSDiv()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10904 SDValue MulRHS = LHS.getOperand(1); in tryFoldToMad64_32() local
10911 bool MulRHSUnsigned32 = numBitsUnsigned(MulRHS, DAG) <= 32; in tryFoldToMad64_32()
10916 numBitsSigned(MulRHS, DAG) <= 32; in tryFoldToMad64_32()
10925 MulRHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulRHS); in tryFoldToMad64_32()
10945 auto MulRHSLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, MulRHS); in tryFoldToMad64_32()
10962 DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, MulRHS, One); in tryFoldToMad64_32()
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