Searched refs:MulLHS (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1226 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0); in emitAddSub() local
1229 if (const auto *C = dyn_cast<ConstantInt>(MulLHS)) in emitAddSub()
1231 std::swap(MulLHS, MulRHS); in emitAddSub()
1235 Register RHSReg = getRegForValue(MulLHS); in emitAddSub()
1595 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0); in emitLogicalOp() local
1598 if (const auto *C = dyn_cast<ConstantInt>(MulLHS)) in emitLogicalOp()
1600 std::swap(MulLHS, MulRHS); in emitLogicalOp()
1605 Register RHSReg = getRegForValue(MulLHS); in emitLogicalOp()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10903 SDValue MulLHS = LHS.getOperand(0); in tryFoldToMad64_32() local
10910 bool MulLHSUnsigned32 = numBitsUnsigned(MulLHS, DAG) <= 32; in tryFoldToMad64_32()
10915 MulSignedLo = numBitsSigned(MulLHS, DAG) <= 32 && in tryFoldToMad64_32()
10924 MulLHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i64, MulLHS); in tryFoldToMad64_32()
10944 auto MulLHSLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, MulLHS); in tryFoldToMad64_32()
10955 DAG.getNode(ISD::EXTRACT_ELEMENT, SL, MVT::i32, MulLHS, One); in tryFoldToMad64_32()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 1871 if (auto *MulLHS = dyn_cast<SCEVConstant>(SM->getOperand(0))) in getZeroExtendExpr() local
1872 if (MulLHS->getAPInt().isPowerOf2()) in getZeroExtendExpr()
1875 MulLHS->getAPInt().logBase2(); in getZeroExtendExpr()
1878 getZeroExtendExpr(MulLHS, Ty), in getZeroExtendExpr()
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