Searched refs:MinPos (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1789 unsigned MinPos = 0; in moveLowLatencies() local
1799 if (PredPos >= MinPos) in moveLowLatencies()
1800 MinPos = PredPos + 1; in moveLowLatencies()
1807 if (BestPos < MinPos) in moveLowLatencies()
1808 BestPos = MinPos; in moveLowLatencies()
1836 if (MinPos < i) { in moveLowLatencies()
1837 for (unsigned u = i; u > MinPos; --u) { in moveLowLatencies()
1841 ScheduledSUnits[MinPos] = SU->NodeNum; in moveLowLatencies()
1842 ScheduledSUnitsInv[SU->NodeNum] = MinPos; in moveLowLatencies()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 43058 SDValue MinPos = Src; in combineMinMaxReduction() local
43063 std::tie(Lo, Hi) = splitVector(MinPos, DAG, DL); in combineMinMaxReduction()
43065 MinPos = DAG.getNode(BinOp, DL, SrcVT, Lo, Hi); in combineMinMaxReduction()
43083 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos); in combineMinMaxReduction()
43091 SrcVT, DL, MinPos, DAG.getConstant(0, DL, MVT::v16i8), in combineMinMaxReduction()
43093 MinPos = DAG.getNode(ISD::UMIN, DL, SrcVT, MinPos, Upper); in combineMinMaxReduction()
43097 MinPos = DAG.getBitcast(MVT::v8i16, MinPos); in combineMinMaxReduction()
43098 MinPos = DAG.getNode(X86ISD::PHMINPOS, DL, MVT::v8i16, MinPos); in combineMinMaxReduction()
43099 MinPos = DAG.getBitcast(SrcVT, MinPos); in combineMinMaxReduction()
43102 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos); in combineMinMaxReduction()
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