| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | MathExtrasTest.cpp | 184 unsigned MaskIdx, MaskLen; in TEST() local
186 EXPECT_TRUE(isShiftedMask_32(0xf0000000, MaskIdx, MaskLen)); in TEST()
188 EXPECT_EQ(4, (int)MaskLen); in TEST()
189 EXPECT_TRUE(isShiftedMask_32(0xffff0000, MaskIdx, MaskLen)); in TEST()
191 EXPECT_EQ(16, (int)MaskLen); in TEST()
192 EXPECT_TRUE(isShiftedMask_32(0xff << 1, MaskIdx, MaskLen)); in TEST()
194 EXPECT_EQ(8, (int)MaskLen); in TEST()
203 unsigned MaskIdx, MaskLen; in TEST() local
207 EXPECT_EQ(4, (int)MaskLen); in TEST()
210 EXPECT_EQ(16, (int)MaskLen); in TEST()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 482 unsigned MaskIdx, MaskLen; in performSRLCombine() local
489 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
497 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
500 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
641 unsigned MaskIdx, MaskLen; in performORCombine() local
644 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
646 CNShamt->getZExtValue() + MaskLen <= ValBits) { in performORCombine()
653 DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT), in performORCombine()
668 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
677 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 580 unsigned &MaskLen) {
584 MaskLen = countPopulation(Value);
593 unsigned &MaskLen) {
597 MaskLen = countPopulation(Value);
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| /llvm-project-15.0.7/llvm/unittests/ADT/ |
| H A D | APIntTest.cpp | 1753 unsigned MaskIdx, MaskLen; in TEST() local
1757 EXPECT_EQ(4, (int)MaskLen); in TEST()
1760 EXPECT_EQ(16, (int)MaskLen); in TEST()
1763 EXPECT_EQ(8, (int)MaskLen); in TEST()
1767 EXPECT_FALSE(APInt(N, 0).isShiftedMask(MaskIdx, MaskLen)); in TEST()
1773 EXPECT_TRUE(MaskVal.isShiftedMask(MaskIdx, MaskLen)); in TEST()
1775 EXPECT_EQ(I, (int)MaskLen); in TEST()
1780 EXPECT_TRUE(MaskVal.isShiftedMask(MaskIdx, MaskLen)); in TEST()
1782 EXPECT_EQ(1, (int)MaskLen); in TEST()
1787 EXPECT_TRUE(MaskVal.isShiftedMask(MaskIdx, MaskLen)); in TEST()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 503 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
505 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
511 MaskLen = Ones; in isShiftedMask()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 998 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
999 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
1042 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
1043 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 956 unsigned MaskLen = SM.Mask.size(); in getOutputSegmentMap() local
957 assert(MaskLen % SegLen == 0); in getOutputSegmentMap()
958 SmallVector<unsigned, 4> Map(MaskLen / SegLen); in getOutputSegmentMap()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3154 unsigned MaskIdx, MaskLen; in performSrlCombine() local
3155 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13684 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13685 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13689 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13690 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13624 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13625 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13629 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13630 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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