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Searched refs:MUL2 (Results 1 – 25 of 52) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dwrap-flags.ll12 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
13 ; CHECK-NEXT: ret i32 [[MUL2]]
26 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
27 ; CHECK-NEXT: ret i32 [[MUL2]]
40 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
41 ; CHECK-NEXT: ret i32 [[MUL2]]
54 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
55 ; CHECK-NEXT: ret i32 [[MUL2]]
68 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
69 ; CHECK-NEXT: ret i32 [[MUL2]]
H A Dcanonicalize-neg-const.ll205 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
206 ; CHECK-NEXT: [[ADD:%.*]] = fadd double [[A]], [[MUL2]]
220 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
221 ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[MUL2]], 5.000000e+00
250 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
251 ; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[A]], [[MUL2]]
265 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
266 ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[MUL2]], 5.000000e+00
400 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[DIV1]], 4.000000e+00
430 ; CHECK-NEXT: [[SUB:%.*]] = fsub double [[A]], [[MUL2]]
[all …]
H A Dmixed-fast-nonfast-fp.ll26 ; CHECK-NEXT: [[MUL2:%.*]] = fmul fast float [[B:%.*]], [[A]]
30 ; CHECK-NEXT: [[ADD2:%.*]] = fadd reassoc float [[MUL2]], [[MUL4]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfmul-2-combine-multi-use.ll44 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
47 ; GCN-DAG: buffer_store_dword [[MUL2]]
60 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
63 ; GCN-DAG: buffer_store_dword [[MUL2]]
150 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
154 ; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
157 ; GCN-DAG: buffer_store_short [[MUL2]]
176 ; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
179 ; GCN-DAG: buffer_store_short [[MUL2]]
202 ; GFX10-FLUSH: v_add_f16_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[MUL2]]
[all …]
H A Dfmuladd.f16.ll84 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
85 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[MUL2]], [[R2]]
114 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
115 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[MUL2]], [[R2]]
186 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
187 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[MUL2]]
217 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
218 ; GFX10-FLUSH: v_sub_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[MUL2]]
244 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
275 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
[all …]
/llvm-project-15.0.7/polly/test/CodeGen/MemAccess/
H A Dcodegen_simple_md.ll60 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
61 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
69 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
70 ; WITHOUTCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
H A Dcodegen_simple_md_float.ll57 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
58 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
66 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
67 ; WITHOUTCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A DPR36280.ll11 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[P2]], [[Y:%.*]]
13 ; CHECK-NEXT: [[ADD2:%.*]] = fadd float [[MUL2]], [[ADD1]]
H A Dcrash_binaryop.ll20 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[ADD2]], 0.000000e+00
21 ; CHECK-NEXT: [[BINARYOP_B:%.*]] = fadd double [[POSTADD1_PHI]], [[MUL2]]
H A Dshuffled-gathers-diff-size.ll10 ; CHECK-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP1]], [[M:%.*]]
11 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL2]], [[MUL]]
/llvm-project-15.0.7/mlir/test/Conversion/TensorToSPIRV/
H A Dtensor-ops-to-spirv.mlir21 // CHECK: %[[MUL2:.+]] = spv.IMul %[[C1]], %[[C]] : i32
22 // CHECK: %[[ADD2:.+]] = spv.IAdd %[[ADD1]], %[[MUL2]] : i32
/llvm-project-15.0.7/llvm/test/Transforms/LoopVersioning/
H A Dwrapping-pointer-versioning.ll34 ; LV-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
35 ; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
36 ; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
159 ; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
160 ; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
263 ; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
264 ; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
361 ; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
362 ; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
468 ; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dscalable-first-order-recurrence.ll27 ; CHECK-VF4UF1: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4
28 ; CHECK-VF4UF1: %[[SUB2:.*]] = sub i32 %[[MUL2]], 1
79 ; CHECK-VF4UF1: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4
80 ; CHECK-VF4UF1: %[[SUB2:.*]] = sub i32 %[[MUL2]], 1
131 ; CHECK-VF4UF1: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4
132 ; CHECK-VF4UF1: %[[SUB2:.*]] = sub i32 %[[MUL2]], 1
217 ; CHECK-VF4UF2: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4
218 ; CHECK-VF4UF2: %[[SUB2:.*]] = sub i32 %[[MUL2]], 1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-mul.mir119 ; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
121 ; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
196 ; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV4]], [[UV7]]
198 ; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
442 ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[MUL2]](s32)
564 ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C1]]
604 ; GFX8-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[MUL2]](s16)
696 ; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
698 ; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
774 ; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV4]]
[all …]
H A Dlegalize-umulh.mir86 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
89 ; GFX8-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
116 ; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
119 ; GFX9-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
160 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV7]]
163 ; GFX8-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
217 ; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV7]]
451 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
452 ; GFX8-NEXT: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[MUL2]], [[C1]](s16)
671 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
[all …]
H A Dlegalize-umulo.mir124 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
127 ; GFX8-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
167 ; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
170 ; GFX9-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
226 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV7]]
229 ; GFX8-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
311 ; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV5]], [[UV7]]
746 ; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[AND6]]
754 ; GFX8-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
788 ; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[AND6]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dmul.mir216 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
218 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
265 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
267 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
268 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
366 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
369 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfmul.ll352 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[MUL]], [[SUB1]]
353 ; CHECK-NEXT: ret float [[MUL2]]
365 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[MUL]], [[SUB1]]
366 ; CHECK-NEXT: ret float [[MUL2]]
452 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[SQRT]], [[F]]
453 ; CHECK-NEXT: ret double [[MUL2]]
552 ; CHECK-NEXT: ret float [[MUL2]]
565 ; CHECK-NEXT: ret float [[MUL2]]
579 ; CHECK-NEXT: ret float [[MUL2]]
594 ; CHECK-NEXT: ret float [[MUL2]]
[all …]
H A Dreassociate-nuw.ll71 ; CHECK-NEXT: [[MUL2:%.*]] = mul nuw i32 [[MUL1]], 45
72 ; CHECK-NEXT: ret i32 [[MUL2]]
H A Dmul-inseltpoison.ll674 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL]], [[NEG]]
675 ; CHECK-NEXT: ret i32 [[MUL2]]
1078 ; CHECK-NEXT: [[MUL2:%.*]] = shl i32 [[MUL1_NEG]], 2
1079 ; CHECK-NEXT: ret i32 [[MUL2]]
1091 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1092 ; CHECK-NEXT: ret i32 [[MUL2]]
1105 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1106 ; CHECK-NEXT: ret i32 [[MUL2]]
1120 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1121 ; CHECK-NEXT: ret i32 [[MUL2]]
H A Dmul.ll886 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL]], [[NEG]]
887 ; CHECK-NEXT: ret i32 [[MUL2]]
1246 ; CHECK-NEXT: [[MUL2:%.*]] = shl i32 [[MUL1_NEG]], 2
1247 ; CHECK-NEXT: ret i32 [[MUL2]]
1259 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1260 ; CHECK-NEXT: ret i32 [[MUL2]]
1273 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1274 ; CHECK-NEXT: ret i32 [[MUL2]]
1288 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1289 ; CHECK-NEXT: ret i32 [[MUL2]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalizer-combiner.mir107 ; CHECK: [[MUL2:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[UV1]]
109 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MUL1]], [[MUL2]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopDistribute/
H A Dscev-inserted-runtime-check.ll17 ; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])
18 ; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
19 ; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
151 ; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])
152 ; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
153 ; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/PowerPC/
H A Dprefer-fma.ll34 ; CHECK-NEXT: [[MUL2:%.*]] = fsub fast double [[TMP6]], [[TMP7]]
35 ; CHECK-NEXT: store double [[MUL2]], double* [[Y]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/IROutliner/
H A Doutlining-branches-phi-nodes.ll151 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 2, [[B2VAL]]
165 ; CHECK-NEXT: store i32 [[MUL2]], i32* [[TMP3]], align 4

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