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Searched refs:MIb (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp326 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
539 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
544 Pair.second.insert(MIb); in runOnMachineFunction()
568 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
569 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
582 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
583 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
597 (void)MIb; in runOnMachineFunction()
598 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
615 LoopStack.back().second.insert(MIb); in runOnMachineFunction()
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H A DSIInstrInfo.cpp3165 assert(MIb.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
3181 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()
3182 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3184 return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb); in areMemAccessesTriviallyDisjoint()
3188 if (isMUBUF(MIb) || isMTBUF(MIb)) in areMemAccessesTriviallyDisjoint()
3189 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3191 return !isFLAT(MIb) && !isSMRD(MIb); in areMemAccessesTriviallyDisjoint()
3195 if (isSMRD(MIb)) in areMemAccessesTriviallyDisjoint()
3196 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3198 return !isFLAT(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb); in areMemAccessesTriviallyDisjoint()
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H A DSIInstrInfo.h140 const MachineInstr &MIb) const;
333 const MachineInstr &MIb) const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp582 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
587 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
596 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
610 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
622 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
628 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
629 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
631 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
632 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
651 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
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H A DHexagonMCCompound.cpp336 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
338 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
346 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
H A DHexagonMCInstrInfo.h241 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
278 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
H A DLanaiInstrInfo.h39 const MachineInstr &MIb) const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h293 const MachineInstr &MIb) const override;
365 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
H A DHexagonInstrInfo.cpp1978 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
1980 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1985 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1998 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB)) in areMemAccessesTriviallyDisjoint()
2000 const MachineOperand &BaseB = MIb.getOperand(BasePosB); in areMemAccessesTriviallyDisjoint()
2009 unsigned SizeB = getMemAccessSize(MIb); in areMemAccessesTriviallyDisjoint()
2013 const MachineOperand &OffB = MIb.getOperand(OffsetPosB); in areMemAccessesTriviallyDisjoint()
2015 !MIb.getOperand(OffsetPosB).isImm()) in areMemAccessesTriviallyDisjoint()
2018 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm(); in areMemAccessesTriviallyDisjoint()
2250 const MachineInstr &MIb) const { in isDuplexPair()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h127 const MachineInstr &MIb) const override;
H A DRISCVInstrInfo.cpp1186 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
1188 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
1190 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1191 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1204 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h362 const MachineInstr &MIb) const override;
H A DSystemZInstrInfo.cpp2020 const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
2022 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) in areMemAccessesTriviallyDisjoint()
2030 MachineMemOperand *MMOb = *MIb.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1796 const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1799 assert(MIb.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h58 const MachineInstr &MIb) const override;
H A DAArch64LoadStoreOptimizer.cpp1210 for (MachineInstr *MIb : MemInsns) in mayAlias()
1211 if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false)) in mayAlias()
H A DAArch64InstrInfo.cpp1044 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
1052 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
1054 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1055 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1067 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, OffsetBIsScalable, in areMemAccessesTriviallyDisjoint()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h655 const MachineInstr &MIb) const override;
H A DPPCInstrInfo.cpp5541 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
5543 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
5545 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
5546 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
5559 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()