| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 335 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
337 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
341 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
346 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| H A D | HexagonMCDuplexInfo.cpp | 573 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
586 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
595 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
617 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
651 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
652 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
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| H A D | HexagonMCInstrInfo.h | 241 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
277 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
90 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
106 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| H A D | LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 292 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
365 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
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| H A D | HexagonInstrInfo.cpp | 1978 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1980 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1985 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1990 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA)) in areMemAccessesTriviallyDisjoint()
1992 const MachineOperand &BaseA = MIa.getOperand(BasePosA); in areMemAccessesTriviallyDisjoint()
2008 unsigned SizeA = getMemAccessSize(MIa); in areMemAccessesTriviallyDisjoint()
2012 const MachineOperand &OffA = MIa.getOperand(OffsetPosA); in areMemAccessesTriviallyDisjoint()
2014 if (!MIa.getOperand(OffsetPosA).isImm() || in areMemAccessesTriviallyDisjoint()
2017 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm(); in areMemAccessesTriviallyDisjoint()
2249 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa, in isDuplexPair() argument
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 126 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | RISCVInstrInfo.cpp | 1186 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1187 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
1190 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1191 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1203 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 361 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | SystemZInstrInfo.cpp | 2019 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
2022 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) in areMemAccessesTriviallyDisjoint()
2029 MachineMemOperand *MMOa = *MIa.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1795 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
1797 assert(MIa.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 3152 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
3156 unsigned Width0 = MIa.memoperands().front()->getSize(); in checkInstOffsetsDoNotOverlap()
3163 assert(MIa.mayLoadOrStore() && in areMemAccessesTriviallyDisjoint()
3180 if (isDS(MIa)) { in areMemAccessesTriviallyDisjoint()
3182 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3187 if (isMUBUF(MIa) || isMTBUF(MIa)) { in areMemAccessesTriviallyDisjoint()
3189 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3194 if (isSMRD(MIa)) { in areMemAccessesTriviallyDisjoint()
3196 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
3201 if (isFLAT(MIa)) { in areMemAccessesTriviallyDisjoint()
[all …]
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| H A D | SIInstrInfo.h | 139 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
332 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 57 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | AArch64LoadStoreOptimizer.cpp | 1207 static bool mayAlias(MachineInstr &MIa, in mayAlias() argument
1211 if (MIa.mayAlias(AA, *MIb, /*UseTBAA*/ false)) in mayAlias()
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| H A D | AArch64InstrInfo.cpp | 1044 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
1051 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
1054 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1055 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1065 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, OffsetAIsScalable, in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 654 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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| H A D | PPCInstrInfo.cpp | 5541 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
5542 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
5545 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
5546 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
5558 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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