| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 93 def MIMG {
102 bit HAS_GFX11 = !ne(gfx11, MIMG.NOP);
104 bit HAS_VI = !ne(vi, MIMG.NOP);
105 bit HAS_SI = !ne(si, MIMG.NOP);
193 let MIMG = 1;
205 class MIMG <dag outs, string dns = "">
222 let FilterClass = "MIMG";
279 : MIMG<outs, dns>, MIMGe_gfx10<op> {
293 : MIMG<outs, dns>, MIMGe_gfx10<op> {
1236 // MIMG Instructions
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| H A D | SILoadStoreOptimizer.cpp | 79 MIMG, enumerator
174 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
407 return MIMG; in getInstClass()
671 if (InstClass == MIMG) { in setMI()
687 } else if (InstClass != MIMG) { in setMI()
797 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
870 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
1032 if (CI.InstClass == MIMG) { in checkAndPrepareMerge()
1692 case MIMG: in getNewOpcode()
1702 assert((CI.InstClass != MIMG || (countPopulation(CI.DMask | Paired.DMask) == in getSubRegIdxs()
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| H A D | SIPostRABundler.cpp | 61 SIInstrFlags::FLAT | SIInstrFlags::MIMG;
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| H A D | SIInstrFormats.td | 42 field bit MIMG = 0;
177 let TSFlags{20} = MIMG;
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| H A D | AMDGPUInsertDelayAlu.cpp | 46 SIInstrFlags::FLAT | SIInstrFlags::MIMG | in instructionWaitsForVALU()
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| H A D | SIDefines.h | 57 MIMG = 1 << 20, enumerator
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| H A D | SIInstrInfo.h | 500 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
504 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| H A D | AMDGPU.td | 237 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
243 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
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| H A D | SIInstrInfo.cpp | 4774 (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) { in adjustAllocatableRegClass()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 269 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
303 MCID.TSFlags & SIInstrFlags::MIMG; in isVMEM()
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| /llvm-project-15.0.7/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1013.rst | 36 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX7.rst | 242 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX8.rst | 243 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX90a.rst | 300 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX9.rst | 331 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX10.rst | 557 MIMG section in Instructions
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| H A D | AMDGPUAsmGFX1030.rst | 533 MIMG section in Instructions
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 350 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3563 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDataSize()
3603 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10Plus()) in validateMIMGAddrSize()
3652 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGAtomicDMask()
3690 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGMSAA()
3845 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGD16()
3861 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDim()
4313 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateAGPRLdSt()
4470 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx10_mimg.txt | 4 # MIMG, regular address
309 # MIMG, NSA address
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 648 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { in getInstruction()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUModifierSyntax.rst | 382 MIMG Modifiers
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 545 bit DA = 0; // DA bit in MIMG encoding
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