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Searched refs:MFFS (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dsetrnd.ll21 ; AFTER-FINALIZE-ISEL: MFFS implicit $rm
42 ; AFTER-FINALIZE-ISEL: MFFS implicit $rm
H A Dnofpexcept.ll99 ; CHECK-NEXT: [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
103 ; CHECK-NEXT: MTFSFb 1, [[MFFS]], implicit-def $rm
140 ; CHECK-NEXT: [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm
H A Dread-set-flm.ll25 ; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
60 ; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h305 MFFS, enumerator
H A DPPCISelLowering.cpp1705 case PPCISD::MFFS: return "PPCISD::MFFS"; in getTargetNodeName()
8778 SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain); in LowerFLT_ROUNDS_() local
8779 Chain = MFFS.getValue(1); in LowerFLT_ROUNDS_()
8784 DAG.getNode(ISD::BITCAST, dl, MVT::i64, MFFS)); in LowerFLT_ROUNDS_()
8789 Chain = DAG.getStore(Chain, dl, MFFS, StackSlot, MachinePointerInfo()); in LowerFLT_ROUNDS_()
12776 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg); in EmitInstrWithCustomInserter()
12841 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
12924 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
12977 BuildMI(*BB, MI, Dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
H A DP10InstrResources.td1157 MFFS,
H A DP9InstrResources.td1103 (instregex "MFFS(L|CE|_rec)?$")
H A DPPCInstrFormats.td758 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
H A DPPCInstrInfo.td184 def PPCmffs : SDNode<"PPCISD::MFFS",
2681 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
3034 def : Pat<(int_ppc_readflm), (MFFS)>;
H A DPPCInstrInfo.cpp2179 if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF) in isSchedulingBoundary()