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/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dbulk-memory64.ll25 ; BULK-MEM-NEXT: return
36 ; BULK-MEM-NEXT: return
47 ; BULK-MEM-NEXT: return
57 ; BULK-MEM-NEXT: return
67 ; BULK-MEM-NEXT: return
77 ; BULK-MEM-NEXT: return
107 ; BULK-MEM-NEXT: return
118 ; BULK-MEM-NEXT: return
129 ; BULK-MEM-NEXT: return
140 ; BULK-MEM-NEXT: return
[all …]
H A Dbulk-memory.ll24 ; BULK-MEM-NEXT: return
34 ; BULK-MEM-NEXT: return
44 ; BULK-MEM-NEXT: return
54 ; BULK-MEM-NEXT: return
64 ; BULK-MEM-NEXT: return
74 ; BULK-MEM-NEXT: return
104 ; BULK-MEM-NEXT: return
115 ; BULK-MEM-NEXT: return
126 ; BULK-MEM-NEXT: return
137 ; BULK-MEM-NEXT: return
[all …]
H A Dtarget-features-tls.ll13 ; NO-BULK-MEM-NEXT: .int8 2
14 ; NO-BULK-MEM-NEXT: .int8 43
15 ; NO-BULK-MEM-NEXT: .int8 7
17 ; NO-BULK-MEM-NEXT: .int8 45
18 ; NO-BULK-MEM-NEXT: .int8 10
24 ; BULK-MEM-NEXT: .int8 2
25 ; BULK-MEM-NEXT: .int8 43
26 ; BULK-MEM-NEXT: .int8 7
28 ; BULK-MEM-NEXT: .int8 43
29 ; BULK-MEM-NEXT: .int8 11
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-unroll.mlir20 // UNROLL-BY-2-SAME: %[[MEM:.*3]]: memref<?xf32>
38 // UNROLL-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV]]] : memref<?xf32>
42 // UNROLL-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[V10]]] : memref<?xf32>
45 // UNROLL-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV]]] : memref<?xf32>
53 // UNROLL-BY-3-SAME: %[[MEM:.*3]]: memref<?xf32>
104 // UNROLL-OUTER-BY-2-SAME: %[[MEM:.*6]]: memref<?xf32>
139 // UNROLL-INNER-BY-2-SAME: %[[MEM:.*6]]: memref<?xf32>
168 // UNROLL-BY-2-SAME: %[[MEM:.*0]]: memref<?xf32>
201 // UNROLL-BY-3-SAME: %[[MEM:.*0]]: memref<?xf32>
237 // UNROLL-BY-3-SAME: %[[MEM:.*0]]: memref<?xf32>
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-to-vector-load-store.mlir4 // CHECK-SAME: %[[MEM:.*]]: memref<f32>
9 // CHECK-NEXT: %[[s:.*]] = memref.load %[[MEM]][] : memref<f32>
14 // CHECK-NEXT: memref.store %[[ss]], %[[MEM]][] : memref<f32>
18 // CHECK-NEXT: memref.store %[[VV]], %[[MEM]][] : memref<f32>
44 // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
62 // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
119 // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
139 // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
197 // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
214 // CHECK-SAME: %[[MEM:.*]]: memref<?x?xf32>,
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Ddma-generate.mlir566 } // FAST-MEM-16KB: }
567 } // FAST-MEM-16KB: }
568 } // FAST-MEM-16KB: }
611 // FAST-MEM-16KB: affine.dma_wait
614 // FAST-MEM-16KB: affine.dma_wait
616 // FAST-MEM-16KB: affine.dma_wait
620 // FAST-MEM-16KB: }
621 // FAST-MEM-16KB: }
622 // FAST-MEM-16KB: }
623 // FAST-MEM-16KB: }
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dlowerheap.ll17 ; IS________OPM-NEXT: [[MEM:%.*]] = call noalias i8* @malloc(i64 [[LEN]])
18 ; IS________OPM-NEXT: [[RES:%.*]] = call i64 @subfn(i8* [[MEM]]) #[[ATTR4:[0-9]+]]
19 ; IS________OPM-NEXT: call void @free(i8* [[MEM]])
41 ; IS________OPM-NEXT: [[MEM:%.*]] = call noalias i8* @calloc(i64 [[LEN]], i64 noundef 8)
42 ; IS________OPM-NEXT: [[RES:%.*]] = call i64 @subfn(i8* [[MEM]]) #[[ATTR4]]
43 ; IS________OPM-NEXT: call void @free(i8* [[MEM]])
H A Dvalue-simplify.ll1654 …ias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[MEM:%.*]]) #[[ATTR8:[0-…
1655 ; IS__TUNIT_OPM-NEXT: [[L:%.*]] = load i32, i32* [[MEM]], align 4
1672 …ias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[MEM:%.*]]) #[[ATTR11:[0…
1673 ; IS__CGSCC_OPM-NEXT: [[L:%.*]] = load i32, i32* [[MEM]], align 4
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dpr42638-VMOVRRDCombine.ll28 ; CHECK-NEXT: Creating new node: {{.*}} i32,ch = load<(load (s32) from [[MEM:%.*]] + 4)>
30 ; CHECK: (load (s32) from [[MEM]] + 4)
31 ; CHECK-NOT: (store (s32) into [[MEM]] + 4)
/llvm-project-15.0.7/llvm/test/Transforms/LICM/
H A Dpromote-tls.ll19 ; CHECK-NEXT: [[MEM:%.*]] = call noalias dereferenceable(16) i8* @malloc(i64 16)
20 ; CHECK-NEXT: [[ADDR:%.*]] = bitcast i8* [[MEM]] to i32*
82 ; CHECK-NEXT: [[MEM:%.*]] = alloca i8, i32 16, align 1
83 ; CHECK-NEXT: [[ADDR:%.*]] = bitcast i8* [[MEM]] to i32*
146 ; CHECK-NEXT: [[MEM:%.*]] = call noalias dereferenceable(16) i8* @custom_malloc(i64 16)
147 ; CHECK-NEXT: [[ADDR:%.*]] = bitcast i8* [[MEM]] to i32*
210 ; CHECK-NEXT: [[MEM:%.*]] = call dereferenceable(16) i8* @not_malloc(i64 16)
211 ; CHECK-NEXT: [[ADDR:%.*]] = bitcast i8* [[MEM]] to i32*
270 ; CHECK-NEXT: [[MEM:%.*]] = call noalias dereferenceable(16) i8* @malloc(i64 16)
271 ; CHECK-NEXT: [[ADDR:%.*]] = bitcast i8* [[MEM]] to i32*
/llvm-project-15.0.7/mlir/test/Conversion/VectorToLLVM/
H A Dvector-mask-to-llvm.mlir51 // CMP32: %[[MEM:.*]]: memref<?xf32>, %[[OFF:.*]]: index) -> vector<16xf32> {
52 // CMP32: %[[D:.*]] = memref.dim %[[MEM]], %{{.*}} : memref<?xf32>
63 // CMP64: %[[MEM:.*]]: memref<?xf32>, %[[OFF:.*]]: index) -> vector<16xf32> {
64 // CMP64: %[[D:.*]] = memref.dim %[[MEM]], %{{.*}} : memref<?xf32>
/llvm-project-15.0.7/lld/test/wasm/
H A Dshared-memory.yaml9 …x-memory=131072 --features=atomics %t1.o -o - 2>&1 | FileCheck %s --check-prefix SHARED-NO-BULK-MEM
63 # SHARED-NO-BULK-MEM: 'bulk-memory' feature must be used in order to use shared memory
H A Ddriver.s26 # RUN: | FileCheck -check-prefix=SHARED-MEM %s
27 # SHARED-MEM: error: -r and --shared-memory may not be used together
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dmemset-1.ll17 ; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[MEM:%.*]], i8 [[TMP1]], i32 [[SIZE:%…
18 ; CHECK-NEXT: ret i8* [[MEM]]
27 ; CHECK-NEXT: tail call void @llvm.memset.p0i8.i32(i8* align 1 [[MEM:%.*]], i8 [[TMP1]], i32 [[S…
28 ; CHECK-NEXT: ret i8* [[MEM]]
227 ; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[MEM:%.*]], i8 [[TMP1]], i32 [[SIZE:%…
228 ; CHECK-NEXT: ret i8* [[MEM]]
/llvm-project-15.0.7/mlir/test/Conversion/AsyncToLLVM/
H A Dconvert-coro-to-llvm.mlir36 // CHECK: %[[MEM:.*]] = llvm.intr.coro.free %[[ID]], %[[HDL]]
37 // CHECK: llvm.call @free(%[[MEM]])
H A Dconvert-to-llvm.mlir63 // CHECK: %[[MEM:.*]] = llvm.intr.coro.free
64 // CHECK: llvm.call @free(%[[MEM]])
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Ddebug-prologue.ll5 ; CHECK: memw([[MEM:.*]]) = r{{[0-9]+}}
6 ; CHECK: r{{[0-9]+}} = memw([[MEM]])
/llvm-project-15.0.7/lld/test/ELF/linkerscript/
H A Dmemory-attr.test34 MEM (a) : org = 0x2000, l = 1K
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToLLVM/
H A Dmemref-to-llvm.mlir116 // CHECK: %[[MEM:.*]]: memref<{{.*}}>,
121 // CHECK32: %[[MEM:.*]]: memref<{{.*}}>,
126 // CHECK-DAG: %[[MEMREF:.*]] = builtin.unrealized_conversion_cast %[[MEM]]
181 // CHECK: %[[MEM:.*]]: memref<{{.*}}>,
186 // CHECK32: %[[MEM:.*]]: memref<{{.*}}>,
245 // CHECK-SAME: %[[MEM:.*]]: memref<{{.*}}>,
250 // CHECK32-SAME: %[[MEM:.*]]: memref<{{.*}}>,
313 // CHECK-SAME: %[[MEM:.*]]: memref<{{.*}}>,
318 // CHECK32-SAME: %[[MEM:.*]]: memref<{{.*}}>,
409 // CHECK: %[[MEM:.*]]: memref<{{.*}}>,
[all …]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dnormalize-memrefs.mlir20 // CHECK: [[MEM:%[0-9]+]] = memref.alloc() : memref<256x64xf32>
23 // CHECK-NEXT: affine.load [[MEM]][%[[J]], %[[I]]] : memref<256x64xf32>
27 // CHECK-NEXT: memref.dealloc [[MEM]]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtransform-patterns.mlir13 linalg.dot { __internal_linalg_transform__ = "MEM" }
55 linalg.matmul { __internal_linalg_transform__ = "MEM" }
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dcanonicalize.mlir187 // CHECK-SAME: %[[MEM:[0-9a-z]+]]: memref<*xf32>
188 // CHECK-NEXT: %[[RANK:.*]] = memref.rank %[[MEM]] : memref<*xf32>
202 // CHECK-SAME: %[[MEM:[0-9a-z]+]]: memref<*xf32>,
224 // CHECK-SAME: %[[MEM:[0-9a-z]+]]: memref<*xf32>,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td247 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
H A DGCNHazardRecognizer.cpp600 int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) { in checkSoftClauseHazards() argument
606 bool IsSMRD = TII.isSMRD(*MEM); in checkSoftClauseHazards()
638 if (MEM->mayStore()) in checkSoftClauseHazards()
641 addClauseInst(*MEM); in checkSoftClauseHazards()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td99 /* MEM */ SDTCisVT<0, iPTR>,
602 // load: What load operation is used with MEM

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