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Searched refs:MCSchedClassDesc (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h46 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
59 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
102 const MCSchedClassDesc *SC = nullptr) const;
105 const MCSchedClassDesc *SC = nullptr) const;
109 const MCSchedClassDesc *SC = nullptr) const;
133 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
137 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
H A DMachineTraceMetrics.h66 struct MCSchedClassDesc;
288 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
289 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
H A DScheduleDAGInstrs.h44 struct MCSchedClassDesc;
265 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
H A DScheduleDAG.h39 struct MCSchedClassDesc;
253 const MCSchedClassDesc *SchedClass =
H A DMachineScheduler.h761 std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
791 unsigned countResource(const MCSchedClassDesc *SC, unsigned PIdx,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp85 const MCSchedClassDesc *SC) const { in mustBeginGroup()
96 const MCSchedClassDesc *SC) const { in mustEndGroup()
107 const MCSchedClassDesc *SC) const { in getNumMicroOps()
131 const MCSchedClassDesc *TargetSchedModel::
135 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
216 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
228 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
255 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
281 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
311 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
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H A DMachineCombiner.cpp117 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
431 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
435 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
456 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
457 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
462 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC); in preservesResourceLen()
463 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC); in preservesResourceLen()
H A DMachineTraceMetrics.cpp122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1225 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1226 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1233 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1237 for (const MCSchedClassDesc *SC : Instrs) { in getResourceLength()
H A DMachineScheduler.cpp2025 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU); in init()
2101 SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx, in getNextResourceCycle()
2186 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2343 unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx, in countResource()
2391 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2627 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSchedule.h109 struct MCSchedClassDesc { struct
306 const MCSchedClassDesc *SchedClassTable;
346 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
355 const MCSchedClassDesc &SCDesc);
364 const MCSchedClassDesc &SCDesc);
H A DMCSubtargetInfo.h168 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
172 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
176 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
184 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
206 getReadAdvanceEntries(const MCSchedClassDesc &SC) const { in getReadAdvanceEntries()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp41 const MCSchedClassDesc &SCDesc) { in computeInstrLatency()
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
89 const MCSchedClassDesc &SCDesc) { in getReciprocalThroughput()
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
171 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
272 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
341 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
390 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
418 const MCSchedClassDesc *SC = SchedModel->resolveSchedClass(MI); in emitInstruction()
H A DSystemZHazardRecognizer.h121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
H A DSystemZMachineScheduler.cpp254 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp42 const MCSchedClassDesc &SCDesc, in initializeUsedResources()
251 const MCSchedClassDesc &SCDesc, in computeMaxLatency()
298 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
569 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
570 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in createInstrDescImpl()
666 const MCSchedClassDesc &SCDesc = in createInstruction()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.h52 const MCSchedClassDesc *const SCDesc;
H A DSchedClassResolution.cpp50 getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc, in getNonRedundantWriteProcRes()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp48 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
1021 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); in GenSchedClassTables()
1027 MCSchedClassDesc &SCDesc = SCTab.back(); in GenSchedClassTables()
1047 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
1093 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1126 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1194 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1215 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1331 std::vector<MCSchedClassDesc> &SCTab = in EmitSchedClassTables()
1344 << MCSchedClassDesc::InvalidNumMicroOps in EmitSchedClassTables()
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/llvm-project-15.0.7/llvm/test/TableGen/
H A DInvalidMCSchedClassDesc.td2 // Check if it is valid MCSchedClassDesc if didn't have the resources.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp86 const MCSchedClassDesc *SCDesc = in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp229 const MCSchedClassDesc *SCDesc = in shouldReplaceInst()
234 const MCSchedClassDesc *SCDescRepl; in shouldReplaceInst()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp508 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in collectWrites()
576 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in checkRAWHazards()
639 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp134 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in collectData()
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp209 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()

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