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Searched refs:MCRegisterClass (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h66 const MCRegisterClass *GPR32RegClass;
67 const MCRegisterClass *GPR64RegClass;
68 const MCRegisterClass *FGR32RegClass;
69 const MCRegisterClass *FGR64RegClass;
70 const MCRegisterClass *AFGR64RegClass;
71 const MCRegisterClass *MSA128BRegClass;
72 const MCRegisterClass *COP0RegClass;
73 const MCRegisterClass *COP2RegClass;
74 const MCRegisterClass *COP3RegClass;
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h31 class MCRegisterClass {
137 using regclass_iterator = const MCRegisterClass *;
160 const MCRegisterClass *Classes; // Pointer to the regclass array
355 const MCRegisterClass *C, unsigned NC, in InitMCRegisterInfo()
466 const MCRegisterClass *RC) const;
543 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass()
548 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.h45 const MCRegisterClass &RegClass);
H A DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp25 const MCRegisterClass *RC) const { in getMatchingSuperReg()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp108 const MCRegisterClass *GPR64RegClass = in hasLiveDefs()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp79 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
533 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); in clearsSuperRegisters()
534 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); in clearsSuperRegisters()
535 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); in clearsSuperRegisters()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h25 class MCRegisterClass; variable
878 unsigned getRegBitWidth(const MCRegisterClass &RC);
H A DAMDGPUBaseInfo.cpp1846 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()
2085 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr15031.ll96 …type { %"struct.llvm::MCRegisterDesc"*, i32, i32, i32, %"class.llvm::MCRegisterClass"*, i32, i32, …
98 %"class.llvm::MCRegisterClass" = type { i8*, i16*, i8*, i16, i16, i16, i16, i16, i8, i8 }
201 %"class.llvm::TargetRegisterClass" = type { %"class.llvm::MCRegisterClass"*, i32*, i32*, i16*, %"cl…
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h52 const MCRegisterClass *MC;
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp169 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); in addRegisterFile()
/llvm-project-15.0.7/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp82 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; in toDREG()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2632 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
4306 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4346 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4347 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4420 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp263 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); in printInst()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1403 const MCRegisterClass &FPR128RC = in printVectorList()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3361 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()
3362 const MCRegisterClass *RC_out = in addMVEVecListOperands()
4503 const MCRegisterClass *RC; in parseRegisterList()
4933 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()
6990 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
7446 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp6920 const MCRegisterClass &WRegClass = in tryParseGPRSeqPair()
6922 const MCRegisterClass &XRegClass = in tryParseGPRSeqPair()