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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dshift-mask.ll47 ; X64-MASK: # %bb.0:
52 ; X64-MASK-NEXT: retq
75 ; X64-MASK: # %bb.0:
80 ; X64-MASK-NEXT: retq
128 ; X64-MASK-NEXT: retq
157 ; X64-MASK-NEXT: retq
201 ; X64-MASK-NEXT: retq
227 ; X64-MASK-NEXT: retq
272 ; X64-MASK-NEXT: retq
300 ; X64-MASK-NEXT: retq
[all …]
H A Dvec_uint_to_fp.ll43 ; SSE: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
44 ; SSE-NEXT: pand %xmm0, [[MASK]]
45 ; After this instruction, MASK will have the value of the low parts
47 ; SSE-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]]
51 ; SSE-NEXT: addps [[MASK]], %xmm0
102 ; SSE: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]
104 ; SSE-NEXT: pand %[[MASK]], [[VECLOW]]
113 ; MASK is the low vector of the second part after this point.
114 ; SSE-NEXT: pand %xmm1, %[[MASK]]
115 ; SSE-NEXT: por %[[LOWCST]], %[[MASK]]
[all …]
H A Dvec_uint_to_fp-fastmath.ll44 ; SSE2: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
45 ; SSE2-NEXT: pand %xmm0, [[MASK]]
46 ; After this instruction, MASK will have the value of the low parts
48 ; SSE2-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]]
52 ; SSE2-NEXT: addps [[MASK]], %xmm0
119 ; SSE2: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]
121 ; SSE2-NEXT: pand %[[MASK]], [[VECLOW]]
130 ; MASK is the low vector of the second part after this point.
131 ; SSE2-NEXT: pand %xmm1, %[[MASK]]
132 ; SSE2-NEXT: por %[[LOWCST]], %[[MASK]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dget-lowbitmask-upto-and-including-bit.ll11 ; CHECK-NEXT: ret i8 [[MASK]]
24 ; CHECK-NEXT: ret i16 [[MASK]]
85 ; CHECK-NEXT: ret i8 [[MASK]]
99 ; CHECK-NEXT: ret i8 [[MASK]]
114 ; CHECK-NEXT: ret i8 [[MASK]]
131 ; CHECK-NEXT: ret i8 [[MASK]]
147 ; CHECK-NEXT: ret i8 [[MASK]]
163 ; CHECK-NEXT: ret i8 [[MASK]]
179 ; CHECK-NEXT: ret i8 [[MASK]]
196 ; CHECK-NEXT: ret i8 [[MASK]]
[all …]
H A Dashr-demand.ll9 ; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], 2
10 ; CHECK-NEXT: ret i32 [[MASK]]
23 ; CHECK-NEXT: [[MASK:%.*]] = select i1 [[ISNEG]], i32 2, i32 0
24 ; CHECK-NEXT: ret i32 [[MASK]]
35 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SREM]], <i32 2, i32 2>
36 ; CHECK-NEXT: ret <2 x i32> [[MASK]]
47 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SREM]], <i32 2, i32 2>
48 ; CHECK-NEXT: ret <2 x i32> [[MASK]]
H A Dnegated-bitmask.ll120 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 2
121 ; CHECK-NEXT: [[NEG:%.*]] = sub nsw i8 0, [[MASK]]
145 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], <i32 1, i32 1>
146 ; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i32> zeroinitializer, [[MASK]]
159 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 1
160 ; CHECK-NEXT: [[NEG:%.*]] = sub nsw i8 0, [[MASK]]
161 ; CHECK-NEXT: call void @usei8(i8 [[MASK]])
175 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], <i32 1, i32 1>
176 ; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i32> zeroinitializer, [[MASK]]
H A Dselect-masked_gather.ll7 …2.nxv2p0f32(<vscale x 2 x float*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 …
18 …i32.nxv2p0i32(<vscale x 2 x i32*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 …
29 …i32.nxv2p0i32(<vscale x 2 x i32*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 …
30 ; CHECK-NEXT: [[MASKED:%.*]] = select <vscale x 2 x i1> [[MASK]], <vscale x 2 x i32> [[GATHER]],…
41 ; CHECK-NEXT: [[MASK:%.*]] = xor <vscale x 2 x i1> [[INV_MASK:%.*]], shufflevector (<vscale x 2 …
42 …i32.nxv2p0i32(<vscale x 2 x i32*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK]], <vscale x 2 x i3…
55 ; CHECK-NEXT: [[MASK:%.*]] = xor <vscale x 2 x i1> [[INV_MASK:%.*]], shufflevector (<vscale x 2 …
56 …i32.nxv2p0i32(<vscale x 2 x i32*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK]], <vscale x 2 x i3…
70 …i32.nxv2p0i32(<vscale x 2 x i32*> [[PTR:%.*]], i32 4, <vscale x 2 x i1> [[MASK]], <vscale x 2 x i3…
98 ; CHECK-NEXT: [[PG:%.*]] = and <vscale x 2 x i1> [[MASK]], [[COND:%.*]]
[all …]
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dext-int-shift.cl9 // CHECK: %[[MASK:.+]] = and i32 %[[PROM]], 31
10 // CHECK: shl i32 77, %[[MASK]]
14 // CHECK: %[[MASK:.+]] = urem i12 %[[PROM]], 12
15 // CHECK: shl i12 %{{.+}}, %[[MASK]]
19 // CHECK: %[[MASK:.+]] = and i32 %[[PROM]], 31
20 // CHECK: shl i32 %{{.+}}, %[[MASK]]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dx86-shuffle-sink-inseltpoison.ll15 ; CHECK-SSE2-NEXT: ret <16 x i8> [[MASK]]
25 ; CHECK-XOP-NEXT: ret <16 x i8> [[MASK]]
34 ; CHECK-AVX-NEXT: ret <16 x i8> [[MASK]]
56 ; CHECK-SSE2-NEXT: ret <8 x i16> [[MASK]]
66 ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
75 ; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
106 ; CHECK-NEXT: ret <4 x i32> [[MASK]]
137 ; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]]
146 ; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]]
177 ; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]]
[all …]
H A Dx86-shuffle-sink.ll15 ; CHECK-SSE2-NEXT: ret <16 x i8> [[MASK]]
25 ; CHECK-XOP-NEXT: ret <16 x i8> [[MASK]]
34 ; CHECK-AVX-NEXT: ret <16 x i8> [[MASK]]
56 ; CHECK-SSE2-NEXT: ret <8 x i16> [[MASK]]
66 ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
75 ; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
106 ; CHECK-NEXT: ret <4 x i32> [[MASK]]
137 ; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]]
146 ; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]]
177 ; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmatch.ll9 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match_any_sync_i32_param_0];
12 ; CHECK: match.any.sync.b32 [[V0:%r[0-9]+]], [[VALUE]], [[MASK]];
16 ; CHECK: match.any.sync.b32 [[V2:%r[0-9]+]], 2, [[MASK]];
28 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match_any_sync_i64_param_0];
31 ; CHECK: match.any.sync.b64 [[V0:%r[0-9]+]], [[VALUE]], [[MASK]];
35 ; CHECK: match.any.sync.b64 [[V2:%r[0-9]+]], 2, [[MASK]];
50 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match_all_sync_i32p_param_0];
53 ; CHECK: match.all.sync.b32 {{%r[0-9]+\|%p[0-9]+}}, [[VALUE]], [[MASK]];
58 ; CHECK: match.all.sync.b32 {{%r[0-9]+\|%p[0-9]+}}, 1, [[MASK]];
86 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [match_all_sync_i64p_param_0];
[all …]
H A Dshfl-sync-p.ll15 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
38 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
41 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]]|[[OUTP:%p[0-9]+]], [[A]], [[B]], 1, [[MASK]];
59 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
80 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
82 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]]|[[OUTP:%p[0-9]+]], [[A]], 1, 2, [[MASK]];
101 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
124 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
145 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
166 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
[all …]
H A Dfns.ll8 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]], [fns_param_0];
12 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], [[OFFSET]];
14 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], 0;
17 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, [[OFFSET]];
19 ; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, 0;
H A Dshfl-sync.ll15 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
19 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], [[C]], [[MASK]];
38 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
41 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], 1, [[MASK]];
59 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
62 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 1, [[C]], [[MASK]];
80 ; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
82 ; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 1, 2, [[MASK]];
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dadd_vp.ll13 ….add.v2i32(<2 x i32> <i32 3, i32 3>, <2 x i32> <i32 7, i32 7>, <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
23 …> @llvm.vp.sub.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
24 …call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[Z]], <2 x i32> [[Y]], <2 x i1> [[MASK]], i32 [[EVL]])
38 …<2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[Z]], <2 x i32> [[Y]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
50 …> @llvm.vp.sub.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
62 …m.vp.sub.v2i32(<2 x i32> zeroinitializer, <2 x i32> [[X:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
63 …l <2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[NEGX]], <2 x i32> [[X]], <2 x i1> [[MASK]], i32 [[EVL]])
80 … i8> @llvm.vp.sub.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.…
81 …] = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> [[Y]], <2 x i8> [[X]], <2 x i1> [[MASK]], i32 [[EVL]])
82 …= call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> [[XY]], <2 x i8> [[YX]], <2 x i1> [[MASK]], i32 [[EVL]])
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dbitwise-ops-to-llvm.mlir50 // CHECK: %[[MASK:.*]] = llvm.xor %[[T2]], %[[MINUS_ONE]] : i32
51 // CHECK: %[[NEW_BASE:.*]] = llvm.and %[[BASE]], %[[MASK]] : i32
67 // CHECK: %[[MASK:.*]] = llvm.xor %[[T2]], %[[MINUS_ONE]] : i64
68 // CHECK: %[[NEW_BASE:.*]] = llvm.and %[[BASE]], %[[MASK]] : i64
84 // CHECK: %[[MASK:.*]] = llvm.xor %[[T2]], %[[MINUS_ONE]] : i16
85 // CHECK: %[[NEW_BASE:.*]] = llvm.and %[[BASE]], %[[MASK]] : i16
196 // CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : i32
198 // CHECK: llvm.and %[[SHIFTED_BASE]], %[[MASK]] : i32
212 // CHECK: llvm.and %[[SHIFTED_BASE]], %[[MASK]] : i32
223 // CHECK: %[[MASK:.*]] = llvm.xor %[[T0]], %[[MINUS_ONE]] : i8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dcomplex-int-to-fp.ll43 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
44 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
64 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
65 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
101 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
102 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
120 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
121 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dfirst-order-recurrence-sink-replicate-region.ll25 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
33 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
54 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
113 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
126 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
198 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
274 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
297 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
374 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
392 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
[all …]
H A Dvplan-sink-scalars-and-merge.ll34 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
98 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
117 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
177 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
197 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
670 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
782 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
845 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
867 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
1005 ; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-masked-loadstore.ll8 ; CHECK-NEXT: %[[MASK:.*]] = fcmp ogt <vscale x 4 x float> %[[LOAD1]],
11 …ed.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
14 …x 4 x float> %[[FADD]], <vscale x 4 x float>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
45 ; CHECK-NEXT: %[[MASK:.*]] = icmp ne <vscale x 4 x i32> %[[LOAD1]],
48 …sked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
51 …ale x 4 x i32> %[[FADD]], <vscale x 4 x i32>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.wqm.vote.ll44 ;WAVE64: s_andn2_b64 [[MASK:[^,]+]], [[EXEC:[^,]+]], [[KILL]]
45 ;WAVE64: s_and_b64 exec, exec, [[MASK]]
49 ;WAVE32: s_and{{n2|_not1}}_b32 [[MASK:[^,]+]], [[EXEC:[^,]+]], [[KILL]]
50 ;WAVE32: s_and_b32 exec_lo, exec_lo, [[MASK]]
H A Dinsert_vector_elt.v2i16.subtest-saddr.ll12 ; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]]
15 ; CI-DAG: v_lshl_b32_e32 [[MASK:v[0-9]+]], 0xffff, [[SCALED_IDX]]
17 ; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VEC]]
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToSPIRV/
H A Dmemref-to-spirv.mlir132 // CHECK: %[[MASK:.+]] = spv.Constant 255 : i32
133 // CHECK: %[[T1:.+]] = spv.BitwiseAnd %[[VALUE]], %[[MASK]] : i32
157 // CHECK: %[[MASK:.+]] = spv.Constant 255 : i32
158 // CHECK: %[[T1:.+]] = spv.BitwiseAnd %[[VALUE]], %[[MASK]] : i32
184 // CHECK: %[[MASK:.+]] = spv.Constant 65535 : i32
185 // CHECK: %[[T1:.+]] = spv.BitwiseAnd %[[VALUE]], %[[MASK]] : i32
222 // CHECK: %[[MASK:.+]] = spv.Not %[[TMP1]] : i32
249 // CHECK: %[[MASK:.+]] = spv.Not %[[TMP1]] : i32
278 // CHECK: %[[MASK:.+]] = spv.Not %[[TMP1]] : i32
332 // CHECK: %[[MASK:.+]] = spv.Constant 255 : i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AtomicExpand/AMDGPU/
H A Dexpand-atomic-i16.ll40 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
41 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
62 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
63 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
72 ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[NEW]], [[MASK]]
96 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
97 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
117 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
118 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
175 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
[all …]
H A Dexpand-atomic-i8.ll40 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
41 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
62 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
63 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
72 ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[NEW]], [[MASK]]
96 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
97 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
117 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
118 ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
175 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
[all …]

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