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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dfloat-store.s45 # M4-NEXT: Total Cycles: 3203
46 # M4-NEXT: Total uOps: 3000
57 # M4-NEXT: uOps Per Cycle: 0.94
58 # M4-NEXT: IPC: 0.69
59 # M4-NEXT: Block RThroughput: 12.5
98 # M4-NEXT: 1 1 0.50 * stur d0, [sp, #2]
100 # M4-NEXT: 1 1 0.50 * str b0, [sp], #1
101 # M4-NEXT: 1 1 0.50 * str q0, [sp], #16
104 # M4-NEXT: 1 1 0.50 * str s0, [sp, #4]
108 # M4-NEXT: 1 1 0.50 * str b0, [sp, x0]
[all …]
H A Dfloat-load.s50 # M4-NEXT: Total Cycles: 4708
51 # M4-NEXT: Total uOps: 3200
62 # M4-NEXT: uOps Per Cycle: 0.68
63 # M4-NEXT: IPC: 0.51
64 # M4-NEXT: Block RThroughput: 13.0
107 # M4-NEXT: 1 5 0.50 * ldur d0, [sp, #2]
109 # M4-NEXT: 1 5 0.50 * ldr b0, [sp], #1
110 # M4-NEXT: 1 5 0.50 * ldr q0, [sp], #16
113 # M4-NEXT: 1 5 0.50 * ldr s0, [sp, #4]
117 # M4-NEXT: 1 5 0.50 * ldr b0, [sp, x0]
[all …]
H A Dasimd-ld1.s52 # M4-NEXT: Total Cycles: 14703
62 # M4-NEXT: uOps Per Cycle: 0.69
63 # M4-NEXT: IPC: 0.24
117 # M4-NEXT: 2 6 1.00 * ld1 { v0.s }[0], [sp]
118 # M4-NEXT: 1 5 0.50 * ld1r { v0.2s }, [sp]
119 # M4-NEXT: 1 5 0.50 * ld1 { v0.2s }, [sp]
123 # M4-NEXT: 2 6 1.00 * ld1 { v0.d }[0], [sp]
124 # M4-NEXT: 1 5 0.50 * ld1r { v0.2d }, [sp]
125 # M4-NEXT: 1 5 0.50 * ld1 { v0.2d }, [sp]
131 # M4-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], #8
[all …]
H A Dasimd-st1.s48 # M4-NEXT: Total Cycles: 6603
49 # M4-NEXT: Total uOps: 8600
60 # M4-NEXT: uOps Per Cycle: 1.30
61 # M4-NEXT: IPC: 0.45
62 # M4-NEXT: Block RThroughput: 33.0
109 # M4-NEXT: 1 1 0.50 * st1 { v0.s }[0], [sp]
110 # M4-NEXT: 1 1 0.50 * st1 { v0.2s }, [sp]
114 # M4-NEXT: 1 1 0.50 * st1 { v0.d }[0], [sp]
115 # M4-NEXT: 1 1 0.50 * st1 { v0.2d }, [sp]
120 # M4-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], #8
[all …]
H A Dasimd-ld2.s34 # M4-NEXT: Total Cycles: 9803
45 # M4-NEXT: uOps Per Cycle: 0.55
46 # M4-NEXT: IPC: 0.18
47 # M4-NEXT: Block RThroughput: 30.0
82 # M4-NEXT: 3 6 1.00 * ld2 { v0.s, v1.s }[0], [sp]
83 # M4-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp]
84 # M4-NEXT: 2 10 3.00 * ld2 { v0.2s, v1.2s }, [sp]
85 # M4-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp]
86 # M4-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp]
87 # M4-NEXT: 2 10 3.00 * ld2 { v0.2d, v1.2d }, [sp]
[all …]
H A Dstore.s23 # M4-NEXT: Total uOps: 1100
29 # M4-NEXT: uOps Per Cycle: 0.84
35 # M4-NEXT: Block RThroughput: 5.5
60 # M4-NEXT: 1 1 0.50 * stur x0, [sp, #8]
61 # M4-NEXT: 1 1 0.50 * strb w0, [sp], #1
62 # M4-NEXT: 1 1 0.50 * strh w0, [sp, #2]!
63 # M4-NEXT: 1 1 0.50 * str x0, [sp, #8]
64 # M4-NEXT: 1 1 0.50 * strb w0, [sp, xzr]
68 # M4-NEXT: 1 1 0.50 * stnp w0, w1, [sp, #8]
69 # M4-NEXT: 1 1 0.50 * stp x0, x1, [sp], #16
[all …]
H A Dasimd-st2.s30 # M4-NEXT: Total Cycles: 2403
31 # M4-NEXT: Total uOps: 2300
42 # M4-NEXT: uOps Per Cycle: 0.96
43 # M4-NEXT: IPC: 0.50
44 # M4-NEXT: Block RThroughput: 7.5
73 # M4-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp]
74 # M4-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp]
75 # M4-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp]
76 # M4-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp]
82 # M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x0
[all …]
H A Dasimd-ld3.s34 # M4-NEXT: Total Cycles: 11804
45 # M4-NEXT: uOps Per Cycle: 0.64
46 # M4-NEXT: IPC: 0.15
47 # M4-NEXT: Block RThroughput: 54.0
82 # M4-NEXT: 4 7 1.50 * ld3 { v0.s, v1.s, v2.s }[0], [sp]
83 # M4-NEXT: 3 6 1.50 * ld3r { v0.2s, v1.2s, v2.2s }, [sp]
84 # M4-NEXT: 3 12 4.50 * ld3 { v0.2s, v1.2s, v2.2s }, [sp]
85 # M4-NEXT: 5 7 4.50 * ld3 { v0.d, v1.d, v2.d }[0], [sp]
86 # M4-NEXT: 3 6 1.50 * ld3r { v0.2d, v1.2d, v2.2d }, [sp]
87 # M4-NEXT: 3 12 4.50 * ld3 { v0.2d, v1.2d, v2.2d }, [sp]
[all …]
H A Dasimd-st3.s30 # M4-NEXT: Total Cycles: 3903
31 # M4-NEXT: Total uOps: 5000
42 # M4-NEXT: uOps Per Cycle: 1.28
43 # M4-NEXT: IPC: 0.31
44 # M4-NEXT: Block RThroughput: 21.0
73 # M4-NEXT: 2 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp]
74 # M4-NEXT: 4 4 2.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp]
75 # M4-NEXT: 2 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp]
76 # M4-NEXT: 6 5 3.00 * st3 { v0.2d, v1.2d, v2.2d }, [sp]
81 # M4-NEXT: 3 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp], x0
[all …]
H A Dasimd-ld4.s34 # M4-NEXT: Total Cycles: 13004
45 # M4-NEXT: uOps Per Cycle: 0.72
46 # M4-NEXT: IPC: 0.14
47 # M4-NEXT: Block RThroughput: 61.5
82 # M4-NEXT: 5 7 2.00 * ld4 { v0.s, v1.s, v2.s, v3.s }[0], [sp]
83 # M4-NEXT: 4 6 2.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
84 # M4-NEXT: 4 14 6.00 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
85 # M4-NEXT: 6 7 3.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[0], [sp]
86 # M4-NEXT: 4 6 2.00 * ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
87 # M4-NEXT: 4 14 6.00 * ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
[all …]
H A Dasimd-st4.s30 # M4-NEXT: Total Cycles: 4803
31 # M4-NEXT: Total uOps: 4700
42 # M4-NEXT: uOps Per Cycle: 0.98
43 # M4-NEXT: IPC: 0.25
44 # M4-NEXT: Block RThroughput: 24.0
73 # M4-NEXT: 2 2 1.00 * st4 { v0.s, v1.s, v2.s, v3.s }[0], [sp]
74 # M4-NEXT: 4 4 2.00 * st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
75 # M4-NEXT: 2 2 1.00 * st4 { v0.d, v1.d, v2.d, v3.d }[0], [sp]
76 # M4-NEXT: 5 8 4.00 * st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
81 # M4-NEXT: 3 2 1.00 * st4 { v0.s, v1.s, v2.s, v3.s }[0], [sp], x0
[all …]
H A Dcrc.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
16 # M4-NEXT: Total Cycles: 404
27 # M4-NEXT: uOps Per Cycle: 0.99
28 # M4-NEXT: IPC: 0.99
29 # M4-NEXT: Block RThroughput: 4.0
50 # M4-NEXT: 1 2 1.00 crc32w w0, w1, w2
51 # M4-NEXT: 1 2 1.00 crc32w w0, w0, w3
52 # M4-NEXT: 1 2 1.00 crc32cx w0, w1, x2
53 # M4-NEXT: 1 2 1.00 crc32cx w0, w0, x3
H A Ddirect-branch.s3 …rch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
12 # M4-NEXT: Total Cycles: 18
22 # M4: Dispatch Width: 6
23 # M4-NEXT: uOps Per Cycle: 5.56
24 # M4-NEXT: IPC: 5.56
25 # M4-NEXT: Block RThroughput: 0.2
43 # M4-NEXT: 1 0 0.17 b main
H A Daes.s3 …rch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
16 # M4-NEXT: Total Cycles: 203
26 # M4-NEXT: uOps Per Cycle: 1.97
27 # M4-NEXT: IPC: 1.97
49 # M4-NEXT: 1 1 0.50 aese v0.16b, v1.16b
50 # M4-NEXT: 1 1 0.50 aesmc v0.16b, v0.16b
51 # M4-NEXT: 1 1 0.50 aesd v0.16b, v1.16b
52 # M4-NEXT: 1 1 0.50 aesimc v0.16b, v0.16b
H A Dfloat-rsqrt.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
23 # M4-NEXT: Total Cycles: 2303
34 # M4-NEXT: uOps Per Cycle: 0.43
35 # M4-NEXT: IPC: 0.43
36 # M4-NEXT: Block RThroughput: 2.0
53 # M4-NEXT: 1 8 1.75 fsqrt s30, s30
61 # M4-NEXT: 1 7 1.50 fdiv s30, s31, s30
62 # M4-NEXT: 1 3 0.50 frsqrte s1, s0
H A Ddouble-rsqrt.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
26 # M4-NEXT: Total Cycles: 3303
37 # M4-NEXT: uOps Per Cycle: 0.39
38 # M4-NEXT: IPC: 0.39
39 # M4-NEXT: Block RThroughput: 3.0
56 # M4-NEXT: 1 12 2.25 fsqrt d30, d30
64 # M4-NEXT: 1 12 2.25 fdiv d30, d31, d30
65 # M4-NEXT: 1 3 0.50 frsqrte d1, d0
H A Dfloat-sqrt.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
24 # M4-NEXT: Total Cycles: 3103
35 # M4-NEXT: uOps Per Cycle: 0.39
36 # M4-NEXT: IPC: 0.35
37 # M4-NEXT: Block RThroughput: 2.3
56 # M4-NEXT: 1 8 1.75 fsqrt s31, s31
57 # M4-NEXT: 1 3 0.50 frsqrte s1, s0
72 # M4-NEXT: 2 5 1.00 fcsel s0, s0, s1, eq
H A Dfloat-recp.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
20 # M4-NEXT: Total Cycles: 1703
31 # M4-NEXT: uOps Per Cycle: 0.41
32 # M4-NEXT: IPC: 0.41
33 # M4-NEXT: Block RThroughput: 1.5
53 # M4-NEXT: 1 7 1.50 fdiv s30, s31, s30
54 # M4-NEXT: 1 3 0.50 frecpe s1, s0
H A Ddouble-sqrt.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
27 # M4-NEXT: Total Cycles: 4103
38 # M4-NEXT: uOps Per Cycle: 0.37
39 # M4-NEXT: IPC: 0.34
40 # M4-NEXT: Block RThroughput: 3.3
59 # M4-NEXT: 1 12 2.25 fsqrt d31, d31
60 # M4-NEXT: 1 3 0.50 frsqrte d1, d0
78 # M4-NEXT: 2 5 1.00 fcsel d0, d0, d1, eq
H A Ddouble-recp.s3 … -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
22 # M4-NEXT: Total Cycles: 2403
33 # M4-NEXT: uOps Per Cycle: 0.37
34 # M4-NEXT: IPC: 0.37
35 # M4-NEXT: Block RThroughput: 2.3
55 # M4-NEXT: 1 12 2.25 fdiv d30, d31, d30
56 # M4-NEXT: 1 3 0.50 frecpe d1, d0
H A Dscheduler-queue-usage.s3 …r-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M4
18 # M4: Dispatch Width: 6
19 # M4-NEXT: uOps Per Cycle: 0.50
20 # M4-NEXT: IPC: 0.50
21 # M4-NEXT: Block RThroughput: 0.2
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dbigoutput.c10 #define M4 M2 M2 M2 M2 macro
11 #define M6 M4 M4 M4 M4
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Ddarwin-eabi.ll2 …UN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
4 ; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
12 ; CHECK-M4-LABEL: float_op:
13 ; CHECK-M4: vadd.f32
22 ; CHECK-M4-LABEL: double_op:
23 ; CHECK-M4: {{(bl|blx|b.w)}} ___adddf3
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dmul.ll47 ; M4: mult $4, $5
48 ; M4: mflo $[[T0:[0-9]+]]
50 ; M4: negu $2, $[[T0]]
88 ; M4: mult $4, $5
89 ; M4: mflo $[[T0:[0-9]+]]
129 ; M4: mult $4, $5
130 ; M4: mflo $[[T0:[0-9]+]]
158 ; M4: mult $4, $5
159 ; M4: mflo $1
202 ; M4: dmult $4, $5
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dcmpy-round.ll26 %v3 = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 -2147483648, i32 -2147483648)
28 %v4 = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 2147483647, i32 2147483647)
30 %v5 = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 -2147483648, i32 -2147483648)
38 declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32) #1
41 declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) #1
44 declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) #1

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