Searched refs:M0Val (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 817 Register M0Val = MI.getOperand(6).getReg(); in selectInterpP1F16() local
818 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) || in selectInterpP1F16()
835 .addReg(M0Val); in selectInterpP1F16()
1357 Register M0Val = MI.getOperand(2).getReg(); in selectDSOrderedIntrinsic() local
1359 .addReg(M0Val); in selectDSOrderedIntrinsic()
1369 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI)) in selectDSOrderedIntrinsic()
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| H A D | SIISelLowering.cpp | 8260 SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(3)); in LowerINTRINSIC_VOID() local
8281 Ops.push_back(M0Val.getValue(0)); // Chain in LowerINTRINSIC_VOID()
8282 Ops.push_back(M0Val.getValue(1)); // Glue in LowerINTRINSIC_VOID()
8324 SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(3)); in LowerINTRINSIC_VOID() local
8359 Ops.push_back(M0Val.getValue(0)); // Chain in LowerINTRINSIC_VOID()
8360 Ops.push_back(M0Val.getValue(1)); // Glue in LowerINTRINSIC_VOID()
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