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Searched refs:LoadLatency (Results 1 – 25 of 72) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleZnver3.td48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
645 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
756 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1228 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
1359 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMPSYrr.Latency);
1373 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
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/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV69.td33 let LoadLatency = 1;
H A DHexagonScheduleV62.td30 let LoadLatency = 1;
H A DHexagonScheduleV55.td41 let LoadLatency = 1;
H A DHexagonScheduleV65.td33 let LoadLatency = 1;
H A DHexagonScheduleV66.td33 let LoadLatency = 1;
H A DHexagonScheduleV67.td33 let LoadLatency = 1;
H A DHexagonScheduleV5.td39 let LoadLatency = 1;
H A DHexagonScheduleV68.td32 let LoadLatency = 1;
H A DHexagonScheduleV67T.td55 let LoadLatency = 1;
H A DHexagonScheduleV60.td74 let LoadLatency = 1;
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td28 let LoadLatency = 2;
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSchedule.h285 unsigned LoadLatency; member
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp133 ? getSchedModel().LoadLatency + 1 in getMaxBuildIntsCost()
H A DRISCVSchedSiFive7.td15 let LoadLatency = 3;
H A DRISCVSchedRocket.td17 let LoadLatency = 3;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleA2.td160 let LoadLatency = 6; // Optimistic load latency assuming bypass.
H A DPPCScheduleG5.td119 let LoadLatency = 3; // Optimistic load latency assuming bypass.
H A DPPCScheduleE500.td272 let LoadLatency = 5; // Optimistic load latency assuming bypass.
H A DPPCScheduleE500mc.td327 let LoadLatency = 5; // Optimistic load latency assuming bypass.
H A DPPCScheduleE5500.td371 let LoadLatency = 6; // Optimistic load latency assuming bypass.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td22 let LoadLatency = 3; // Optimistic load latency.
H A DAArch64SchedKryo.td22 let LoadLatency = 4; // Optimistic load latency
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM4.td16 let LoadLatency = 2; // Latency when not pipelined, not pc-relative

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