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Searched refs:LoHalf (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp625 return OpRef(R.OpN & (Undef | Index | LoHalf)); in lo()
645 LoHalf = 0x20000000, enumerator
647 Whole = LoHalf | HiHalf,
722 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
723 if (OpN & LoHalf) in print()
1074 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
1077 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo in materialize()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1850 MachineInstr *LoHalf = in computeBase() local
1856 (void)LoHalf; in computeBase()
1857 LLVM_DEBUG(dbgs() << " "; LoHalf->dump();); in computeBase()
H A DSIInstrInfo.cpp6733 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp() local
6753 Worklist.insert(&LoHalf); in splitScalar64BitUnaryOp()
6802 MachineInstr *LoHalf = in splitScalar64BitAddSub() local
6828 legalizeOperands(*LoHalf, MDT); in splitScalar64BitAddSub()
6874 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
6892 Worklist.insert(&LoHalf); in splitScalar64BitBinaryOp()
H A DSIISelLowering.cpp4091 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter() local
4111 TII->legalizeOperands(*LoHalf); in EmitInstrWithCustomInserter()
5688 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
5693 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf); in lowerINSERT_VECTOR_ELT()
5707 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf }); in lowerINSERT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4855 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
4864 .addDef(LoHalf) in emitLDR_D()
4872 .addUse(LoHalf); in emitLDR_D()