Searched refs:Lg2 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4819 unsigned Lg2 = C.countTrailingZeros(); in selectSDiv() local
4825 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2); in selectSDiv()
4832 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv()
4861 AArch64_AM::ASR, Lg2); in selectSDiv()
4863 ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2); in selectSDiv()
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| H A D | AArch64ISelLowering.cpp | 14001 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
14003 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2()
14017 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
14048 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSREMPow2() local
14049 if (Lg2 == 0) in BuildSREMPow2()
14054 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSREMPow2()
14057 if (Lg2 == 1) { in BuildSREMPow2()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12506 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
12507 if (Lg2 == 1 || Lg2 >= 12) in BuildSDIVPow2()
12518 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2()
12531 DAG.getNode(ISD::SRA, DL, VT, Sel, DAG.getConstant(Lg2, DL, VT)); in BuildSDIVPow2()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15862 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros(); in BuildSDIVPow2() local
15863 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT); in BuildSDIVPow2()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23967 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
23970 if (Lg2 == 1) in BuildSDIVPow2()
23976 APInt Lg2Mask = APInt::getLowBitsSet(VT.getSizeInBits(), Lg2); in BuildSDIVPow2()
23990 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8)); in BuildSDIVPow2()
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