| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86LegalizerInfo.cpp | 177 LegacyLegalizeActions::Legal); in setLegalizerInfo32bit()
192 LegacyLegalizeActions::Legal); in setLegalizerInfo32bit()
238 LegacyLegalizeActions::Legal); in setLegalizerInfo64bit()
286 LegacyLegalizeActions::Legal); in setLegalizerInfo64bit()
312 LegacyLegalizeActions::Legal); in setLegalizerInfoSSE1()
318 LegacyLegalizeActions::Legal); in setLegalizerInfoSSE1()
360 LegacyLegalizeActions::Legal); in setLegalizerInfoSSE2()
367 LegacyLegalizeActions::Legal); in setLegalizerInfoSSE2()
371 LegacyLegalizeActions::Legal); in setLegalizerInfoSSE2()
424 LegacyLegalizeActions::Legal); in setLegalizerInfoAVX()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.cpp | 30 case Legal: in operator <<()
71 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
72 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
73 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
74 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
75 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegacyLegalizerInfo()
161 ElementSizesSeen.push_back({ElementSize, Legal}); in computeTables()
256 case Legal: in findAction()
347 if (ElementSizeAndAction.second != Legal) in findVectorLegalAction()
373 if (Action.first != Legal) { in getAction()
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| H A D | LegalizerInfo.cpp | 39 case Legal: in operator <<()
100 case Legal: in hasNoSimpleLoops()
118 if (Rule.getAction() == Custom || Rule.getAction() == Legal) in mutationIsSane()
360 return getAction(MI, MRI).Action == Legal; in isLegal()
368 return Action == Legal || Action == Custom; in isLegalOrCustom()
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerInfoTest.cpp | 25 case Legal: OS << "Legal"; break; in operator <<()
72 LegalizeActionStep(Legal, 0, LLT{})); in TEST()
74 LegalizeActionStep(Legal, 0, LLT{})); in TEST()
99 LegacyLegalizeActions::Legal); in TEST()
101 LegacyLegalizeActions::Legal); in TEST()
103 LegacyLegalizeActions::Legal); in TEST()
122 LegalizeActionStep(Legal, 0, LLT{})); in TEST()
154 LegalizeActionStep(Legal, 0, LLT{})); in TEST()
200 LegalizeActionStep(Legal, 0, LLT{})); in TEST()
446 EXPECT_ACTION(Legal, 0, LLT(), in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 118 setOperationAction(ISD::ADD, MVT::i32, Legal); in ARCTargetLowering()
119 setOperationAction(ISD::SUB, MVT::i32, Legal); in ARCTargetLowering()
120 setOperationAction(ISD::AND, MVT::i32, Legal); in ARCTargetLowering()
121 setOperationAction(ISD::SMAX, MVT::i32, Legal); in ARCTargetLowering()
122 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
124 setOperationAction(ISD::ADDC, MVT::i32, Legal); in ARCTargetLowering()
125 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
130 setOperationAction(ISD::SHL, MVT::i32, Legal); in ARCTargetLowering()
131 setOperationAction(ISD::SRA, MVT::i32, Legal); in ARCTargetLowering()
132 setOperationAction(ISD::SRL, MVT::i32, Legal); in ARCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VPRecipeBuilder.h | 35 LoopVectorizationLegality *Legal; variable
110 LoopVectorizationLegality *Legal, in VPRecipeBuilder() argument
113 : OrigLoop(OrigLoop), TLI(TLI), Legal(Legal), CM(CM), PSE(PSE), in VPRecipeBuilder()
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| H A D | LoopVectorize.cpp | 705 LoopVectorizationLegality *Legal; member in llvm::InnerLoopVectorizer
1144 : ScalarEpilogueStatus(SEL), TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), in LoopVectorizationCostModel()
1380 return Legal->isInductionPhi(Op); in isOptimizableIVTruncate()
1463 return Legal->isMaskRequired(I); in isPredicatedInst()
1798 LoopVectorizationLegality *Legal; member in llvm::LoopVectorizationCostModel
4439 if (!Legal->isMaskRequired(I)) in isScalarWithPredication()
4506 Legal->isMaskRequired(I); in interleavedAccessCanBeWidened()
6373 if (Legal->isMaskRequired(I)) in getConsecutiveMemOpCost()
6390 assert(Legal->isUniformMemOp(*I)); in getUniformMemOpCost()
6767 if (Legal->isUniformMemOp(I)) { in setCostBasedWideningDecision()
[all …]
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| H A D | LoopVectorizationPlanner.h | 266 LoopVectorizationLegality *Legal; variable
288 LoopVectorizationLegality *Legal, in LoopVectorizationPlanner() argument
294 : OrigLoop(L), LI(LI), TLI(TLI), TTI(TTI), Legal(Legal), CM(CM), IAI(IAI), in LoopVectorizationPlanner()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 319 setOperationAction(ISD::LOAD, Ty, Legal); in addMSAIntType()
326 setOperationAction(ISD::ADD, Ty, Legal); in addMSAIntType()
327 setOperationAction(ISD::AND, Ty, Legal); in addMSAIntType()
328 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
330 setOperationAction(ISD::MUL, Ty, Legal); in addMSAIntType()
331 setOperationAction(ISD::OR, Ty, Legal); in addMSAIntType()
334 setOperationAction(ISD::SHL, Ty, Legal); in addMSAIntType()
335 setOperationAction(ISD::SRA, Ty, Legal); in addMSAIntType()
336 setOperationAction(ISD::SRL, Ty, Legal); in addMSAIntType()
337 setOperationAction(ISD::SUB, Ty, Legal); in addMSAIntType()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 169 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
346 setOperationAction(ISD::LOAD, VT, Legal); in SystemZTargetLowering()
347 setOperationAction(ISD::STORE, VT, Legal); in SystemZTargetLowering()
365 setOperationAction(ISD::ADD, VT, Legal); in SystemZTargetLowering()
366 setOperationAction(ISD::SUB, VT, Legal); in SystemZTargetLowering()
369 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
370 setOperationAction(ISD::AND, VT, Legal); in SystemZTargetLowering()
371 setOperationAction(ISD::OR, VT, Legal); in SystemZTargetLowering()
372 setOperationAction(ISD::XOR, VT, Legal); in SystemZTargetLowering()
377 setOperationAction(ISD::CTTZ, VT, Legal); in SystemZTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 199 setTruncStoreAction(MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
200 setTruncStoreAction(MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
236 setOperationAction(ISD::ADDC, VT, Legal); in PPCTargetLowering()
237 setOperationAction(ISD::ADDE, VT, Legal); in PPCTargetLowering()
238 setOperationAction(ISD::SUBC, VT, Legal); in PPCTargetLowering()
239 setOperationAction(ISD::SUBE, VT, Legal); in PPCTargetLowering()
764 setOperationAction(ISD::ADD, VT, Legal); in PPCTargetLowering()
765 setOperationAction(ISD::SUB, VT, Legal); in PPCTargetLowering()
770 setOperationAction(ISD::SMAX, VT, Legal); in PPCTargetLowering()
771 setOperationAction(ISD::SMIN, VT, Legal); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.h | 46 Legal, enumerator
157 case LegacyLegalizeActions::Legal: in LegalizeActionStep()
158 Action = LegalizeActions::Legal; in LegalizeActionStep()
590 return actionIf(LegalizeAction::Legal, Predicate); in legalIf()
594 return actionFor(LegalizeAction::Legal, Types); in legalFor()
599 return actionFor(LegalizeAction::Legal, Types); in legalFor()
605 return actionForTypeWithAnyImm(LegalizeAction::Legal, Types); in legalForTypeWithAnyImm()
611 return actionForTypeWithAnyImm(LegalizeAction::Legal, Types); in legalForTypeWithAnyImm()
619 return actionIf(LegalizeAction::Legal, in legalForTypesWithMemDesc()
646 return actionIf(LegalizeAction::Legal, always); in alwaysLegal()
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | IRSimilarityIdentifier.h | 76 enum InstrType { Legal, Illegal, Invisible }; enumerator
125 bool Legal = false; member
522 return Legal; in visitBranchInst()
527 return Legal; in visitPHINode()
552 return EnableIntrinsics ? Legal : Illegal; in visitIntrinsicInst()
575 return Legal; in visitCallInst()
583 InstrType visitInstruction(Instruction &I) { return Legal; } in visitInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 163 setIndexedLoadAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
164 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
166 setOperationAction(ISD::AND, T, Legal); in initializeHVXLowering()
167 setOperationAction(ISD::OR, T, Legal); in initializeHVXLowering()
168 setOperationAction(ISD::XOR, T, Legal); in initializeHVXLowering()
169 setOperationAction(ISD::ADD, T, Legal); in initializeHVXLowering()
170 setOperationAction(ISD::SUB, T, Legal); in initializeHVXLowering()
171 setOperationAction(ISD::MUL, T, Legal); in initializeHVXLowering()
172 setOperationAction(ISD::CTPOP, T, Legal); in initializeHVXLowering()
264 setOperationAction(ISD::ADD, T, Legal); in initializeHVXLowering()
[all …]
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| H A D | HexagonISelLowering.cpp | 1568 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1572 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
1573 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in HexagonTargetLowering()
1575 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1576 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
1577 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1578 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
1710 setOperationAction(ISD::SMIN, VT, Legal); in HexagonTargetLowering()
1711 setOperationAction(ISD::SMAX, VT, Legal); in HexagonTargetLowering()
1712 setOperationAction(ISD::UMIN, VT, Legal); in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VETargetTransformInfo.h | 117 return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); in getVPLegalizationStrategy()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | atomic-unordered.ll | 585 ; Legal, as expected
632 ; Legal, as expected
673 ; Legal, as expected
943 ; Legal, as expected
1038 ; Legal, as expected
1107 ; Legal, as expected
1157 ; Legal, as expected
1207 ; Legal, as expected
1257 ; Legal, as expected
1310 ; Legal, as expected
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 514 setOperationAction(ISD::ABS, Ty, Legal); in NVPTXTargetLowering()
515 setOperationAction(ISD::SMIN, Ty, Legal); in NVPTXTargetLowering()
516 setOperationAction(ISD::SMAX, Ty, Legal); in NVPTXTargetLowering()
517 setOperationAction(ISD::UMIN, Ty, Legal); in NVPTXTargetLowering()
575 setOperationAction(Op, MVT::f16, Legal); in NVPTXTargetLowering()
576 setOperationAction(Op, MVT::f32, Legal); in NVPTXTargetLowering()
577 setOperationAction(Op, MVT::f64, Legal); in NVPTXTargetLowering()
599 setOperationAction(Op, MVT::f32, Legal); in NVPTXTargetLowering()
600 setOperationAction(Op, MVT::f64, Legal); in NVPTXTargetLowering()
610 setOperationAction(Op, MVT::f32, Legal); in NVPTXTargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | ExpandVectorPredication.cpp | 40 VPINTERNAL_CASE(Legal) \
625 case VPLegalization::Legal: in expandVectorPredication()
635 Job.Strategy.EVLParamStrategy = VPLegalization::Legal; in expandVectorPredication()
639 case VPLegalization::Legal: in expandVectorPredication()
648 Job.Strategy.OpStrategy = VPLegalization::Legal; in expandVectorPredication()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | IRSimilarityIdentifier.cpp | 50 : Inst(&I), Legal(Legality), IDL(&IDList) { in IRInstructionData()
204 if (!A.Legal || !B.Legal) in isClose()
280 case InstrType::Legal: in convertToUnsignedVec()
488 if (!A.Legal || !B.Legal) in isSimilar()
772 if (!ItA->Legal || !ItB->Legal) in compareStructure()
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ |
| H A D | pr37515.ll | 3 ; FP primary induction is not supported in LV. Make sure Legal bails out.
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | fp-intrinsics-fptosi-legal.ll | 4 ; as Legal.
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.h | 189 return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); in getVPLegalizationStrategy()
|
| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/ |
| H A D | consecutive-ptr-cg-bug.ll | 15 ; Legal->isConsecutivePtr() to be consistent and return the same output as
18 ; After D39346, LV code generation doesn't rely on Legal->isConsecutivePtr(),
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 196 Legal, // The target natively supports this operation. enumerator
1088 return Legal; in getCustomOperationAction()
1117 if (Action != Legal) in getFixedPointOperationAction()
1167 (getOperationAction(Op, VT) == Legal ||
1181 (getOperationAction(Op, VT) == Legal ||
1195 (getOperationAction(Op, VT) == Legal ||
1271 getOperationAction(Op, VT) == Legal; in isOperationLegal()
1290 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1322 (getTruncStoreAction(ValVT, MemVT) == Legal || in isTruncStoreLegalOrCustom()
1418 return getCondCodeAction(CC, VT) == Legal; in isCondCodeLegal()
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