Searched refs:Ld2 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | GISelAliasTest.cpp | 39 auto Ld2 = B.buildLoad(S64, Addr2, *LoadMMO); in TEST_F() local 42 EXPECT_TRUE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F() 89 auto Ld2 = B.buildLoad(S64, Addr2, *LoadMMO); in TEST_F() local 93 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F() 94 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld2, *Ld1, *MRI, nullptr)); in TEST_F() 124 auto Ld2 = B.buildLoad(S64, GFI2, *LoadMMO); in TEST_F() local 128 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F()
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/ |
| H A D | intrinsics.ll | 62 %Ld2 = load i64, i64* %src 63 %swp3 = tail call i64 @llvm.bswap.i64(i64 %Ld2) 88 %Ld2 = load <2 x i64>, <2 x i64>* %src 89 %swp3 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld2) 110 %Ld2 = load i32, i32* %src 111 %swp3 = tail call i32 @llvm.bswap.i32(i32 %Ld2) 135 %Ld2 = load <4 x i32>, <4 x i32>* %src 136 %swp3 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %Ld2) 157 %Ld2 = load i16, i16* %src 158 %swp3 = tail call i16 @llvm.bswap.i16(i16 %Ld2) [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMParallelDSP.cpp | 568 auto Ld2 = static_cast<LoadInst*>(PMul0->RHS); in CreateParallelPairs() local 572 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs() 576 if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs() 580 } else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) { in CreateParallelPairs() 587 AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs()
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/ |
| H A D | reduction-small-size.ll | 129 ; CHECK: [[Ld2:%[a-zA-Z0-9.]+]] = load <16 x i8> 130 ; CHECK: zext <16 x i8> [[Ld2]] to <16 x i16>
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| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | shuff-combos-128b.ll | 202 ; CHECK: v[[Hd2:[0-9]+]]:[[Ld2:[0-9]+]] = vdeal(v[[Hd1]],v[[Ld1]],[[Rd2]])
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