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Searched refs:Ld1 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dload-and-test.ll6 %Ld1 = load i64, i64* %Src
7 %Cmp = icmp eq i64 %Ld1, 0
8 %S = select i1 %Cmp, i64 %Arg, i64 %Ld1
11 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Ld1 = load i64, i64* %Src
12 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Cmp = icmp eq i64 %Ld1, 0
17 %Ld1 = load i32, i32* %Src
18 %Cmp = icmp eq i32 %Ld1, 0
19 %S = select i1 %Cmp, i32 %Arg, i32 %Ld1
22 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Ld1 = load i32, i32* %Src
23 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Cmp = icmp eq i32 %Ld1, 0
H A Dintrinsics.ll56 %Ld1 = load i64, i64* %src
57 %swp1 = tail call i64 @llvm.bswap.i64(i64 %Ld1)
82 %Ld1 = load <2 x i64>, <2 x i64>* %src
83 %swp1 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld1)
104 %Ld1 = load i32, i32* %src
105 %swp1 = tail call i32 @llvm.bswap.i32(i32 %Ld1)
129 %Ld1 = load <4 x i32>, <4 x i32>* %src
130 %swp1 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %Ld1)
151 %Ld1 = load i16, i16* %src
152 %swp1 = tail call i16 @llvm.bswap.i16(i16 %Ld1)
[all …]
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DGISelAliasTest.cpp38 auto Ld1 = B.buildLoad(S64, Addr, *LoadMMO); in TEST_F() local
42 EXPECT_TRUE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F()
88 auto Ld1 = B.buildLoad(S64, Addr, *LoadMMO); in TEST_F() local
93 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F()
94 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld2, *Ld1, *MRI, nullptr)); in TEST_F()
99 EXPECT_TRUE(GISelAddressing::instMayAlias(*Ld1, *Ld3, *MRI, nullptr)); in TEST_F()
123 auto Ld1 = B.buildLoad(S64, GFI1, *LoadMMO); in TEST_F() local
128 EXPECT_FALSE(GISelAddressing::instMayAlias(*Ld1, *Ld2, *MRI, nullptr)); in TEST_F()
140 EXPECT_FALSE(GISelAddressing::instMayAlias(*FixedFILd1, *Ld1, *MRI, nullptr)); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp228 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
302 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
304 if (!Ld0 || !Ld1) in AreSequentialLoads()
307 if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1) in AreSequentialLoads()
312 dbgs() << "Ld1:"; Ld1->dump(); in AreSequentialLoads()
317 VecMem.push_back(Ld1); in AreSequentialLoads()
567 auto Ld1 = static_cast<LoadInst*>(PMul1->LHS); in CreateParallelPairs() local
572 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()
575 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) { in CreateParallelPairs()
586 } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) && in CreateParallelPairs()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dreduction-small-size.ll127 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <16 x i8>
128 ; CHECK: zext <16 x i8> [[Ld1]] to <16 x i16>
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dshuff-combos-128b.ll201 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vshuff(v[[Hd0]],v[[Ld0]],[[Rd1]])
202 ; CHECK: v[[Hd2:[0-9]+]]:[[Ld2:[0-9]+]] = vdeal(v[[Hd1]],v[[Ld1]],[[Rd2]])
H A Dshuff-combos-64b.ll187 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vdeal(v[[Hd0]],v[[Ld0]],[[Rd1]])