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Searched refs:Late (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp598 ValueSeq &Late);
1181 ValueSeq &First = !IsE ? Early : Late; in classifyCycle()
1185 ValueSeq &Second = IsE ? Early : Late; in classifyCycle()
1206 if (Late.count(TV) || Late.count(FV)) in classifyInst()
1209 } else if (Late.count(TV) || Late.count(FV)) { in classifyInst()
1212 Late.insert(UseI); in classifyInst()
1226 else if (Late.count(&*I)) in classifyInst()
1246 Late.insert(UseI); in classifyInst()
1319 ValueSeq Early, Late, Cycled; in convertShiftsToLeft() local
1334 classifyCycle(&I, C, Early, Late); in convertShiftsToLeft()
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H A DHexagonInstrFormats.td93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
/llvm-project-15.0.7/llvm/test/YAMLParser/
H A Dspec-02-27.test29 Late afternoon is best.
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSplitKit.h429 bool Late, unsigned RegIdx);
433 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
H A DSplitKit.cpp520 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) { in buildSingleSubRegCopy() argument
530 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildSingleSubRegCopy()
539 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
546 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildCopy()
568 DestLI, Late, Def); in buildCopy()
590 bool Late = RegIdx != 0; in defFromParent() local
603 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); in defFromParent()
624 Def = Indexes.insertMachineInstrInMaps(*ImplicitDef, Late).getRegSlot(); in defFromParent()
627 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
H A DLiveRangeEdit.cpp184 bool Late) { in rematerializeAt() argument
192 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h218 bool Late = false);
H A DSlotIndexes.h534 SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
546 if (Late) {
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DO3-pipeline.ll204 ; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td60 // ALU - Write occurs in Late EX2 (independent of whether shift was required)
78 // Branches - LR written in Late EX2
/llvm-project-15.0.7/llvm/docs/
H A DCodeGenerator.rst145 6. `Late Machine Code Optimizations`_ --- Optimizations that operate on "final"
1589 Late Machine Code Optimizations
H A DWritingAnLLVMBackend.rst52 Insertion, Late Machine Code Optimizations, and Code Emission.