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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx512-fsel.ll20 ; CHECK-NEXT: LBB0_1: ## %L_0
29 br i1 %x11, label %L_0, label %L_1
31 L_0: ; preds = %2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dnew-load-requires-renaming-in-mssa.ll22 ; CHECK-NEXT: [[L_0:%.*]] = load <4 x double>, ptr [[GEP_0]], align 8
25 ; CHECK-NEXT: [[S_0:%.*]] = shufflevector <4 x double> [[L_0]], <4 x double> [[L_4]], <2 x i32> …
27 ; CHECK-NEXT: [[S_1:%.*]] = shufflevector <4 x double> [[L_0]], <4 x double> [[L_4]], <2 x i32> …
29 ; CHECK-NEXT: [[S_2:%.*]] = shufflevector <4 x double> [[L_0]], <4 x double> [[L_4]], <2 x i32> …
31 ; CHECK-NEXT: [[S_3:%.*]] = shufflevector <4 x double> [[L_0]], <4 x double> [[L_4]], <2 x i32> …
/llvm-project-15.0.7/llvm/test/Transforms/GVN/PRE/
H A Dmodified-status.ll9 ; CHECK-NEXT: [[L_0:%.*]] = load i32, i32* [[PTR_1:%.*]], align 4
14 ; CHECK-NEXT: [[L_0_EXT:%.*]] = zext i32 [[L_0]] to i64
24 ; CHECK-NEXT: [[REP_0:%.*]] = phi i32 [ [[L_2]], [[IF_2_THEN]] ], [ [[L_0]], [[IF_END]] ]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A D2009-05-12-externweak.ll29 ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[L_0:%.*]], 1
33 ; CHECK-NEXT: [[L_0]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP4]], [[BB3]] ]
34 ; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[L_0]], 99
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Dmultiblock-loop-carried-dependence.ll30 ; CHECK-NEXT: [[L_0:%.*]] = load i32, i32* [[PTR_IV_2]], align 4
31 ; CHECK-NEXT: call void @use(i32 [[L_0]])
94 ; CHECK-NEXT: [[L_0:%.*]] = load i32, i32* [[PTR_IV_2]], align 4
95 ; CHECK-NEXT: call void @use(i32 [[L_0]])
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dvectorizable-selects-uniform-cmps.ll15 ; CHECK-NEXT: [[L_0:%.*]] = load i16, i16* [[PTR:%.*]], align 2
16 ; CHECK-NEXT: [[CMP_0:%.*]] = icmp ult i16 [[L_0]], 16383
17 ; CHECK-NEXT: [[S_0:%.*]] = select i1 [[CMP_0]], i16 [[L_0]], i16 [[X:%.*]]
109 ; CHECK-NEXT: [[L_0:%.*]] = load i8, i8* [[PTR:%.*]], align 1
110 ; CHECK-NEXT: [[CMP_0:%.*]] = icmp ugt i8 [[L_0]], -1
111 ; CHECK-NEXT: [[S_0:%.*]] = select i1 [[CMP_0]], i8 [[L_0]], i8 [[X:%.*]]
H A Dvectorizable-selects-min-max.ll110 ; CHECK-NEXT: [[L_0:%.*]] = load i32, i32* [[PTR:%.*]], align 4
111 ; CHECK-NEXT: [[CMP_0:%.*]] = icmp ult i32 [[L_0]], 16383
112 ; CHECK-NEXT: [[S_0:%.*]] = select i1 [[CMP_0]], i32 [[L_0]], i32 16383
H A Dmemory-runtime-checks.ll714 ; CHECK-NEXT: [[L_0:%.*]] = load float, float* [[B_GEP_0]], align 8
715 ; CHECK-NEXT: [[ADD_0:%.*]] = fadd float [[L_0]], 1.000000e+01
785 ; CHECK-NEXT: [[L_0:%.*]] = load float, float* [[B_GEP_0]], align 8
786 ; CHECK-NEXT: [[ADD_0:%.*]] = fadd float [[L_0]], 1.000000e+01
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DLoopInfoTest.cpp194 Loop &L_0 = *LI.getLoopFor(&*I++); in TEST() local
195 ASSERT_EQ("loop.0", L_0.getHeader()->getName()); in TEST()
213 EXPECT_EQ(&L_0, Preorder[0]); in TEST()
228 EXPECT_EQ(&L_0, ReverseSiblingPreorder[4]); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ARM/
H A Dmve-reductions.ll1398 ; CHECK-NEXT: [[L_0:%.*]] = load i32, i32* [[GEP_0]], align 4
1401 ; CHECK-NEXT: [[RED_1:%.*]] = add i32 [[L_0]], [[RED_PHI]]