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Searched refs:LWR (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dunaligned-memops.ll16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load (s32) from %ir.a, align 1)
17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store (s32) into %ir.b, align 1)
18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store (s32) into %ir.b, align 1)
H A Dunaligned-memops-mapping.mir61 %4:gpr32 = LWR %0, 3, %2 :: (load (s32) from %ir.a, align 1)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dload_4_unaligned.mir41 …; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load (s32) from @f…
42 ; MIPS32: $f0 = COPY [[LWR]]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp230 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp214 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2712 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2724 return LWR; in lowerLOAD()
2737 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2739 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
4794 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_W()
4863 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
4874 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
H A DMipsISelLowering.h249 LWR, enumerator
H A DMipsInstrInfo.cpp657 case Mips::LWR: in HasLoadDelaySlot()
H A DMipsInstructionSelector.cpp487 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
H A DMipsScheduleP5600.td140 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
H A DMipsScheduleGeneric.td569 def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
H A DMipsInstrInfo.td140 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
2128 def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4520 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()