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Searched refs:LWL (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dunaligned-memops.ll15 ; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load (s32) from %ir.a, align 1)
16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load (s32) from %ir.a, align 1)
H A Dunaligned-memops-mapping.mir60 %2:gpr32 = LWL %0, 0, %3 :: (load (s32) from %ir.a, align 1)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dload_4_unaligned.mir40 …; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load (s32) from @f…
41 …; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load (s32) from @f…
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp229 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.h248 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
H A DMipsISelLowering.cpp213 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2710 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2712 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
4799 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_W()
4868 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
4879 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
H A DMipsInstrInfo.cpp658 case Mips::LWL: in HasLoadDelaySlot()
H A DMipsInstructionSelector.cpp484 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, in select()
H A DMipsScheduleP5600.td140 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
H A DMipsScheduleGeneric.td569 def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
H A DMipsInstrInfo.td138 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
2126 def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4519 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()