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Searched refs:LSU (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td83 def : WriteRes<LSU, [ZEC12_LSUnit]>;
127 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
132 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
212 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
302 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
438 def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
503 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
549 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
576 def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
728 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
[all …]
H A DSystemZScheduleZ196.td82 def : WriteRes<LSU, [Z196_LSUnit]>;
122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
128 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
204 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, EndGroup],
291 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
427 def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
492 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
564 def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
690 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
[all …]
H A DSystemZScheduleZ16.td88 def : WriteRes<LSU, [Z16_LSUnit]>;
236 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
238 def : InstRW<[WLat1, FXb, LSU, NormalGr],
333 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
480 def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
511 def : InstRW<[WLat30, RegReadAdv, FXa2, LSU, GroupAlone2],
545 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
555 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
601 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
705 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
[all …]
H A DSystemZScheduleZ15.td88 def : WriteRes<LSU, [Z15_LSUnit]>;
236 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
238 def : InstRW<[WLat1, FXb, LSU, NormalGr],
333 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
480 def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
545 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
555 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
601 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
705 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
731 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZScheduleZ13.td88 def : WriteRes<LSU, [Z13_LSUnit]>;
234 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
236 def : InstRW<[WLat1, FXb, LSU, NormalGr],
328 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
465 def : InstRW<[WLat6LSU, RegReadAdv, FXa, LSU, NormalGr],
521 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
531 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
577 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
670 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
696 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZScheduleZ14.td88 def : WriteRes<LSU, [Z14_LSUnit]>;
235 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
237 def : InstRW<[WLat1, FXb, LSU, NormalGr],
329 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
466 def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
531 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
541 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
587 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
690 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
716 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZSchedule.td22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
29 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
43 def "LSU"#Num : SchedWrite;
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
87 LSU.onInstructionIssued(IR); in issueInstructionImpl()
95 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
135 if (IS.isMemOp() && !LSU.isReady(IR)) { in promoteToReadySet()
172 if (IS.isMemOp() && LSU.isWaiting(IR)) { in promoteToPendingSet()
233 LSU.onInstructionExecuted(IR); in updateIssuedSet()
256 if (IS.isMemOp() && LSU.isPending(IR)) in analyzeDataDependencies()
268 LSU.cycleEvent(); in cycleEvent()
306 IS.setLSUTokenID(LSU.dispatch(IR)); in dispatch()
314 if (IS.isPending() || (IS.isMemOp() && LSU.isPending(IR))) { in dispatch()
[all …]
/llvm-project-15.0.7/llvm/lib/MCA/
H A DContext.cpp42 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createDefaultPipeline() local
44 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
52 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); in createDefaultPipeline()
57 addHardwareUnit(std::move(LSU)); in createDefaultPipeline()
77 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createInOrderPipeline() local
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU); in createInOrderPipeline()
87 addHardwareUnit(std::move(LSU)); in createInOrderPipeline()
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp48 LSUnit &LSU) in InOrderIssueStage() argument
49 : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU), in InOrderIssueStage()
129 if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) { in canExecute()
201 IS.setLSUTokenID(LSU.dispatch(IR)); in execute()
238 LSU.onInstructionIssued(IR); in tryIssue()
263 LSU.onInstructionExecuted(IR); in tryIssue()
298 LSU.onInstructionExecuted(IR); in updateIssuedInst()
345 LSU.onInstructionRetired(IR); in retireInstruction()
386 LSU.cycleEvent(); in cycleStart()
H A DRetireStage.cpp67 LSU.onInstructionRetired(IR); in notifyInstructionRetired()
/llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/
H A DRetireStage.h32 LSUnitBase &LSU; variable
39 : RCU(R), PRF(F), LSU(LS) {} in RetireStage()
H A DInOrderIssueStage.h59 LSUnit &LSU; variable
116 CustomBehaviour &CB, LSUnit &LSU);
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dpostra-sched-expandedops.mir11 # CHECK-NEXT: ** Available: {SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone, SU(6):LARL/FXa}
12 # CHECK-NEXT: ** Best so far: SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone Grouping cost:-1 Height:43
15 # CHECK-NEXT: ++ HazardRecognizer emitting SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone
17 # CHECK-NEXT: ++ Completed decode group: { SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone } (6 decoder sl…
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h71 LSUnitBase &LSU; variable
167 : LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0), in Scheduler()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td45 // Each LSU pipeline can also execute FX add and logical instructions.
46 // Each LSU pipeline can complete a load or store in one cycle.
48 // Each store is broken into two parts, AGEN goes to the LSU while a
H A DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
257 // op is issued to the LSU, and the data op (register fetch) is issued
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
H A DPPCScheduleE500.td25 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
31 def E500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE500mc.td25 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
35 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE5500.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
38 def E5500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCInstrInfo.td2374 /// that they will fill slots (which could cause the load of a LSU reject to