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/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/ARM/
H A D2012-06-15-lsr-noaddrmode.ll3 ; LSR should only check for valid address modes when the IV user is a
11 ; LSR before the fix:
13 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
15 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
17 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
19 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
21 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
24 ; LSR after the fix:
28 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
30 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/BDCE/
H A Dsext_multi_uses.ll8 ; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 8
9 ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255
26 ; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 8
27 ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255
46 ; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 9
47 ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255
67 ; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 8
68 ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255
85 ; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 8
86 ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 255
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/Power/
H A Dmemory-intrinsic.ll7 ; CHECK: LSR Use: Kind=Address
8 ; CHECK: LSR Use: Kind=Address
9 ; CHECK-NOT: LSR Use: Kind=Basic
10 ; CHECK-NOT: LSR Use: Kind=Basic
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dlsr-insns-2.ll5 ; OPT checks that LSR prefers less instructions to less registers.
6 ; For x86 LSR should prefer complicated address to new lsr induction
20 ; LLC checks that LSR prefers less instructions to less registers.
21 ; LSR should prefer complicated address to additonal add instructions.
H A D2011-11-29-postincphi.ll5 ; LSR first expands %t3 to %t2 in %phi
6 ; LSR then expands %t2 in %phi into two decrements, one on each loop exit.
13 ; Check that LSR did something close to the behavior at the time of the bug.
H A D2011-12-04-loserreg.ll3 ; Test LSR's ability to prune formulae that refer to nonexistent
6 ; Unable to reduce this case further because it requires LSR to exceed
9 ; We really just want to ensure that LSR can process this loop without
12 ; verify that LSR removes it.
H A D2011-07-20-DoubleIV.ll3 ; Test LSR's OptimizeShadowIV. Handle a floating-point IV with a
11 ; First, make sure LSR doesn't crash on an empty IVUsers list.
H A Dcanonical.ll2 ; Check LSR formula canonicalization will put loop invariant regs before
32 ; CHECK-NEXT: [[LSR:%[^,]+]] = phi i64 [ 1, %for.body3.lr.ph ], [ {{.*}}, %for.body3 ]
34 ; CHECK-NEXT: [[LOADADDR:%[^,]+]] = getelementptr i8, i8* {{.*}}, i64 [[LSR]]
H A Dlsr-insns-1.ll6 ; OPT test checks that LSR optimize compare for static counter to compare with 0.
8 ; LLC test checks that LSR optimize compare for static counter.
13 ; LSR should optimize out cmp:
H A Dnested-loop.ll5 ; induction value expr, LSR can still choose to use single induction variable
64 ; Check LSR only generates two induction variables for for.body2 one for compare and
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A D2012-01-02-nopreheader.ll9 ; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*.
13 ; Currently, LSR won't kick in on such loops.
55 ; that LSR picks. We must detect that %bb8.preheader does not have a
56 ; preheader and avoid performing LSR on %bb7.
H A Dpr51329.ll3 ; Test that LSR SCEV-based salvaging does not crash when translating SCEVs
6 ; pre-LSR.
H A Ddbg-preserve-2.ll3 ; Test that LSR does not produce invalid debug info when a debug value is
4 ; salvaged during LSR by adding additional location operands, then becomes
H A Dphi_node_update_multiple_preds.ll2 ; LSR should not crash on this.
H A Dephemeral.ll7 ; // i * a + b is ephemeral and shouldn't be promoted by LSR
H A Dillegal-addr-modes.ll11 ; "[LSR] Narrow search space by filtering non-optimal formulae with the
14 ; Due to a bug in ARMTargetLowering::isLegalAddressingMode LSR got
16 ; Another issue was that LSR got that -1*reg was free for the Thumb1 target.
H A Dmissing-phi-operand-update.ll1 ; PR41445: This test checks the case when LSR split critical edge
13 ; This test checks that LSR is still able to rewrite %tmp2, %tmp3, %tmp4.
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
94 defm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h36 LSR, enumerator
57 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
78 case 1: return AArch64_AM::LSR; in getShiftType()
106 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dloop-strength-reduce-crash.ll3 ; LSR doesn't actually do anything on this input; just check that it doesn't
H A Dloop-hoist.ll1 ; LSR should hoist the load from the "Arr" stub out of the loop.
H A Dlsr-nonaffine.ll3 ; LSR should leave non-affine expressions alone because it currently
H A Dlsr-delayed-fold.ll4 ; but LSR should tolerate this.
53 ; LSR ends up going into conservative pruning mode; don't prune the solution
136 ; LSR needs to remember inserted instructions even in postinc mode, because
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/AArch64/
H A Dsmall-constant.ll4 ; Test LSR for giving small constants, which get re-associated as unfolded
6 ; large constants which do not fit as add immediate operands). LSR
H A Dlsr-reuse.ll5 ; Verify that redundant adds aren't inserted by LSR.

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