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Searched refs:LS1 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1413 LatticeCell LS1; in evaluateANDri() local
1416 if (LS1.isBottom() || LS1.isProperty()) in evaluateANDri()
1480 LatticeCell LS1; in evaluateORri() local
1483 if (LS1.isBottom() || LS1.isProperty()) in evaluateORri()
1536 LatticeCell LS1; in evaluateXORri() local
1569 LatticeCell LS1; in evaluateZEXTr() local
1603 if (LS1.isBottom() || LS1.isProperty()) in evaluateSEXTr()
1668 if (LS1.isBottom() || LS1.isProperty()) in evaluateCLBr()
1703 if (LS1.isBottom() || LS1.isProperty()) in evaluateCTBr()
1797 if (LS1.isBottom() || LS1.isProperty()) in evaluateSplatr()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td290 // 1 cycle on LS0/LS1.
296 // 2 cycles on LS0/LS1.
302 // 4 cycles on LS0/LS1.
309 // 5 cycles on LS0/LS1.
315 // 6 cycles on LS0/LS1.
321 // 4 + 5 cycles on LS0/LS1.
331 // 4 + 8 cycles on LS0/LS1.
404 // 1 cycle on LS0/LS1 and SD.
411 // 2 cycles on LS0/LS1 and SD.
418 // 4 cycles on LS0/LS1 and SD.
[all …]
H A DAArch64SchedThunderX2T99.td213 // 1 cycles on LS0 or LS1.
218 // 1 cycles on LS0 or LS1 and I0, I1, or I2.
231 // 2 cycles on LS0 or LS1.
237 // 4 cycles on LS0 or LS1.
243 // 5 cycles on LS0 or LS1.
249 // 6 cycles on LS0 or LS1.
294 // 1 cycles on LS0 or LS1 and F0 or F1.
300 // 5 cycles on LS0 or LS1 and F0 or F1.
306 // 6 cycles on LS0 or LS1 and F0 or F1.
312 // 7 cycles on LS0 or LS1 and F0 or F1.
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2395 GLoadStore *LS1 = dyn_cast<GLoadStore>(I1); in matchEqualDefs() local
2397 if (!LS1 || !LS2) in matchEqualDefs()
2401 (LS1->getMemSizeInBits() != LS2->getMemSizeInBits())) in matchEqualDefs()