Searched refs:LOAD32 (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | GlobalISelEmitterMatchTableOptimizer.td | 9 def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; 29 …{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD32:{ *:[i8] } GPR32:{… 30 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD32, 40 (LOAD32 GPR32:$src)>;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 98 unsigned LOAD32; member 310 STORE_OPCODE(LOAD32, LDRi12); in OpcodeCache() 368 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32; in selectLoadStoreOpCode() 695 TII.get(Opcodes.LOAD32)) in selectGlobal()
|
| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.td | 943 class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 959 : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | legalize-insert-vector-elt.mir | 715 …; CHECK-NEXT: [[LOAD32:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD30]](p5) :: (load (s32) from unknown-add… 758 …; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD32]](s32), [[LOAD33]](…
|
| H A D | irtranslator-sibling-call.ll | 919 …; GCN-NEXT: [[LOAD32:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX32]](p5) :: (invariant load (s32) fr… 1087 …; GCN-NEXT: [[LOAD32:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX32]](p5) :: (invariant load (s32) fr…
|
| H A D | irtranslator-function-args.ll | 2536 …; CHECK-NEXT: [[LOAD32:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX32]](p5) :: (invariant load (s32) … 2537 …[LOAD27]](s32), [[LOAD28]](s32), [[LOAD29]](s32), [[LOAD30]](s32), [[LOAD31]](s32), [[LOAD32]](s32)
|