Home
last modified time | relevance | path

Searched refs:LINE (Results 1 – 25 of 777) sorted by relevance

12345678910>>...32

/llvm-project-15.0.7/llvm/test/MC/Mips/micromips32r6/
H A Dinvalid.s6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
37 swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid register number
38 swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: invalid register number
62 teq $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number
63 teq $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number
64 tge $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number
66 tgeu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number
68 tlt $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number
70 tltu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number
72 tne $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
7 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
59 swe $33, 8($gp) # CHECK: :[[@LINE]]:7: error: invalid register number
60 swe $2, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
66 lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
67 lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
70 lwe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
71 lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
74 sbe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
78 sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
[all …]
/llvm-project-15.0.7/clang/test/FixIt/
H A Dfixit-availability.mm10 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, *)) {\n "
13 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, *)) {\n "
16 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, *)) {\n "
20 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:5-[[@LINE-1]]:5}:"if (@available(macOS 10.12, *)) {\n "
24 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, *)) {\n "
27 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, *)) {\n "
36 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:5-[[@LINE-1]]:5}:"if (@available(macOS 10.12, *)) {\n "
129 // CHECK: fix-it:{{.*}}:{[[@LINE-2]]:1-[[@LINE-2]]:1}:"API_AVAILABLE(macos(10.12))\n"
132 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:22-[[@LINE-1]]:22}:" API_AVAILABLE(macos(10.12))"
136 // CHECK: fix-it:{{.*}}:{[[@LINE-1]]:1-[[@LINE-1]]:1}:"API_AVAILABLE(macos(10.12))\n"
[all …]
H A Dformat-darwin.m44 // CHECK: fix-it:"{{.*}}":{[[@LINE-5]]:11-[[@LINE-5]]:13}:"%ld"
45 // CHECK: fix-it:"{{.*}}":{[[@LINE-6]]:16-[[@LINE-6]]:16}:"(long)"
47 // CHECK: fix-it:"{{.*}}":{[[@LINE-7]]:11-[[@LINE-7]]:13}:"%lu"
50 // CHECK: fix-it:"{{.*}}":{[[@LINE-9]]:11-[[@LINE-9]]:13}:"%d"
51 // CHECK: fix-it:"{{.*}}":{[[@LINE-10]]:16-[[@LINE-10]]:16}:"(int)"
53 // CHECK: fix-it:"{{.*}}":{[[@LINE-11]]:11-[[@LINE-11]]:13}:"%u"
58 // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:13}:"%ld"
59 // CHECK: fix-it:"{{.*}}":{[[@LINE-3]]:16-[[@LINE-3]]:16}:"(long)"
63 // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:13}:"%ld"
100 // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:13}:"%ld"
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/msa/
H A Dinvalid.s8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
134 insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
135 insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
136 insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
[all …]
H A Dinvalid-64.s8 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
9 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
10 insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
11 insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
12 insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
13 insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
14 insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
18 insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
19 insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
20 insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/virt/
H A Dinvalid.s10 mfgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
11 mfgc0 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
12 mfgc0 $4 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
13 mfgc0 0, $4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
14 mfgc0 0, $4, $5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
15 mfgc0 $4, 0, $5 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
18 mfgc0 $4, $5, 0($4) # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
19 mtgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
20 mtgc0 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
22 mtgc0 0, $4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips-invalid.s6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
7 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
8 addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
31 lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
34 swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
65 cache -1, 8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
66 cache 32, 8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
67 pref -1, 8($5) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
68 pref 32, 8($5) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
80 prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
[all …]
H A Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
272 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
275 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
316 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
[all …]
H A Dset-nomacro.s85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
106 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
110 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
113 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
122 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
131 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
140 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/crc/
H A Dinvalid.s9 crc32b $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
10 crc32b $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
11 crc32b $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
12 crc32b $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
13 crc32b 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
14 crc32b $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
15 crc32b $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
16 crc32b $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
63 crc32 $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
64 crcb $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drva-aliases-invalid.s11 lr.w a1, (foo) # CHECK: :[[@LINE]]:11: error: expected register
12 lr.w a1, 0(foo) # CHECK: :[[@LINE]]:12: error: expected register
15 lr.w a1, 0(a0 # CHECK: :[[@LINE]]:17: error: expected ')'
16 lr.w a1, (a0 # CHECK: :[[@LINE]]:17: error: expected ')'
21 sc.w a2, a1, (foo) # CHECK: :[[@LINE]]:15: error: expected register
22 sc.w a2, a1, 0(foo) # CHECK: :[[@LINE]]:16: error: expected register
25 sc.w a2, a1, 0(a0 # CHECK: :[[@LINE]]:21: error: expected ')'
26 sc.w a2, a1, (a0 # CHECK: :[[@LINE]]:21: error: expected ')'
35 amoswap.w a2, a1, 0(a0 # CHECK: :[[@LINE]]:26: error: expected ')'
45 amoadd.w a2, a1, 0(a0 # CHECK: :[[@LINE]]:25: error: expected ')'
[all …]
H A Dpriv-invalid.s3 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
5 sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
7 sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
9 sinval.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
11 sinval.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
13 sfence.w.inval 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
15 sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
19 hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
23 hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
37 hlv.b a0, 1(a1) # CHECK: :[[@LINE]]:11: error: optional integer offset must be 0
[all …]
H A Drv32c-invalid.s6 c.lw ra, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
7 c.sw sp, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
8 c.beqz t0, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
9 c.bnez s8, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
11 c.srli s7, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
12 c.srai t0, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
13 c.andi t1, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
14 c.and t1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
16 c.xor t2, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
22 c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/dsp/
H A Dinvalid.s4 extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
5 extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
6 extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
7 extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
10 extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
11 extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
12 extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-load-store.s8 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
12 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
16 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
20 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
24 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
28 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
32 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
36 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
40 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
44 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/eva/
H A Dinvalid_R6.s21 lle $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid register number
22 lle $4, 8($33) # CHECK: :[[@LINE]]:25: error: invalid register number
25 lwe $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid register number
26 lwe $4, 8($33) # CHECK: :[[@LINE]]:25: error: invalid register number
29 sbe $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid register number
30 sbe $4, 8($33) # CHECK: :[[@LINE]]:25: error: invalid register number
33 sce $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid register number
34 sce $4, 8($33) # CHECK: :[[@LINE]]:25: error: invalid register number
37 she $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid register number
38 she $4, 8($33) # CHECK: :[[@LINE]]:25: error: invalid register number
[all …]
H A Dinvalid-noeva-wrong-error.s22 … cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
23 … cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
24 … cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
25 …lbe $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
26 …lbe $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
27 …lbe $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
28 …lbue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
29 …lbue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
30 …lbue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
31 …lhe $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
[all …]
H A Dinvalid.s12 lle $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid register number
13 lle $4, 8($33) # CHECK: :[[@LINE]]:15: error: invalid register number
16 lwe $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid register number
17 lwe $4, 8($33) # CHECK: :[[@LINE]]:15: error: invalid register number
20 sbe $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid register number
21 sbe $4, 8($33) # CHECK: :[[@LINE]]:15: error: invalid register number
24 sce $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid register number
25 sce $4, 8($33) # CHECK: :[[@LINE]]:15: error: invalid register number
28 she $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid register number
29 she $4, 8($33) # CHECK: :[[@LINE]]:15: error: invalid register number
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips1/
H A Dinvalid.txt6 0x00 0x11 0x00 0x0f # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
7 0x00 0x30 0xc0 0x42 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
8 0x00 0xab 0x09 0x4a # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
9 0x02 0x80 0x44 0xf0 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
10 0x02 0xc5 0x40 0x01 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
11 0x03 0x21 0x22 0xd5 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
12 0x03 0xa0 0x08 0x13 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
13 0x04 0x1c 0x63 0xee # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
14 0x40 0x3c 0x00 0x5d # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
15 0x42 0x02 0x00 0x27 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
[all …]
/llvm-project-15.0.7/clang/test/Index/
H A Dretain-excluded-conditional-blocks.m3 // CHECK: [[@LINE+1]]:12: ObjCInterfaceDecl=MyCls
10 // CHECK: [[@LINE+1]]:12: ObjCInterfaceDecl=Test1
13 // CHECK: [[@LINE+1]]:12:
18 // CHECK: [[@LINE+1]]:12:
21 // CHECK: [[@LINE+1]]:12: ObjCInterfaceDecl=Test4
26 // CHECK: [[@LINE+1]]:12: ObjCInterfaceDecl=Test5
29 // CHECK: [[@LINE+1]]:12: ObjCInterfaceDecl=Test6
38 // CHECK: [[@LINE+1]]:12:
54 // CHECK: [[@LINE+1]]:12:
81 // CHECK: [[@LINE+1]]:12:
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5.s8 …add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
9 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
11 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
101 … ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
H A Dinvalid-mips4.s8 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
72 … lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/FileCheck/
H A Dline-count.txt28 28 BAD2: [[ @LINE]]
31 31 BAD3: [[@LINE ]]
34 34 BAD4: [[ @LINE-1]]
37 37 BAD5: [[@LINE -1]]
40 40 BAD6: [[@LINE- 1]]
43 43 BAD7: [[@LINE-1 ]]
49 49 BAD9: [[@LINE*2]]
52 52 BAD10: [[@LINE-x]]
57 57 BAD11: [[@LINE-1x]]
71 71 BAD13: [[@LINE-0xA]]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-dsp.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]

12345678910>>...32