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/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst52 ``LDR`` and ``LD1``
58 Big endian vector load using ``LDR``.
75 …1. The content of a vector register is the same *as if* it had been loaded with an ``LDR`` instruc…
95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls.
143 | | ``LDR`` layout | ``LD1`` layout |
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Daarch64-adrp-ldr-got.s20 ## LDR contains a nonzero addend, no relaxations should be applied.
24 ## LDR and ADRP use different registers, no relaxations should be applied.
28 ## LDR and ADRP use different registers, no relaxations should be applied.
65 # RUN: FileCheck --check-prefix=LONE-LDR %s
67 # LONE-LDR: ldr x0
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A D2010-06-14-NEONCoalescer.ll26 ; CHECK: vldr [[LDR:d.*]],
28 ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]]
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S37 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
90 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
139 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
H A Dxray_trampoline_arm.S26 LDR r2, [pc, r1]
58 LDR r2, [pc, r1]
89 LDR r2, [pc, r1]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darm-memory-instructions.s12 @ LDR (immediate)
29 @ FIXME: LDR (literal)
H A Dbasic-thumb-instructions.s260 @ LDR (immediate)
279 @ LDR (literal)
293 @ LDR (register)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-misched-basic-A57.ll12 ; CHECK: LDR
15 ; CHECK: LDR
16 ; CHECK: LDR
17 ; CHECK-NOT: LDR
H A Dglobal-alignment.ll13 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
41 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
H A Darm64-fast-isel-addr-offset.ll6 ; Load an address with an offset larget then LDR imm can handle
H A Darm64-collect-loh.ll404 ; LDR supports loading from a literal.
436 ; LDR float supports loading from a literal.
468 ; LDR half supports loading from a literal.
500 ; LDR double supports loading from a literal.
532 ; LDR 64-bit vector supports loading from a literal.
564 ; LDR 128-bit vector supports loading from a literal.
596 ; LDR 8-bit vector supports loading from a literal.
H A Dextern-weak.ll25 ; In the tiny codemodel we us a got relocated LDR.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2012-06-12-SchedMemLatency.ll12 ; CHECK: SU(3){{.*}}LDR{{.*}}(volatile
22 ; CHECK: SU(3){{.*}}LDR{{.*}}
H A Dipra-no-csr.ll7 ; LDR/STRs in the caller.
/llvm-project-15.0.7/lld/test/MachO/
H A Dloh-adrp-ldr-got-ldr.s64 ## Not an LDR (immediate)
99 ### Transformation to a literal LDR
148 ### Transformation to ADR+LDR
182 ### Transformation to ADRP + immediate LDR
/llvm-project-15.0.7/bolt/test/AArch64/
H A Dskip-got-rel.test1 // This test checks that the binary with relaxed ADRP+LDR instructions is
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-move-12.ll5 ; Test that we use LDR instead of LER.
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/AArch64/
H A DMachO_arm64_relocations.s38 # For the GOTPAGEOFF/LDR instruction we have the 12-bit offset of the entry
78 # For the GOTPAGEOFF12 relocation we test the ADD instruction, all LDR/GPR
79 # variants and all LDR/Neon variants.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td416 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(W|X)l$")>;
419 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)ui$")>;
422 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
501 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[DSQ]l")>;
503 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
504 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ]ui")>;
505 def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
H A DAArch64SchedExynosM3.td522 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
524 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
566 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
569 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
570 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
572 ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
574 ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb1.txt159 # LDR (immediate)
179 # LDR (register)
H A Dmemory-arm-instructions.txt4 # LDR (immediate)
19 # FIXME: LDR (literal)
27 # LDR (register)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-basic-a64-undefined.txt3 # LDR/STR: undefined if option field is 10x or 00x.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DREADME.txt504 Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting
505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
506 ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg)
507 while ARMConstantIslandPass only need to worry about LDR (literal).
H A DARMScheduleA57.td378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate
391 def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;
419 // --- LDR pre-indexed ---
438 (instregex "LDR(H|SH|SB)_PRE")>;
456 // --- LDR post-indexed ---
457 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR(T?)_POST_IMM",
458 "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST")>;
465 (instregex "LDR(H|SH|SB)_POST")>;
470 "LDRB_POST_REG", "LDR(B?)T_POST$")>;
484 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;

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