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Searched refs:LDP (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S48 LDP X8, X0, [SP], #16
49 LDP Q6, Q7, [SP], #32
50 LDP Q4, Q5, [SP], #32
51 LDP Q2, Q3, [SP], #32
52 LDP Q0, Q1, [SP], #32
53 LDP X7, X30, [SP], #16
54 LDP X5, X6, [SP], #16
55 LDP X3, X4, [SP], #16
56 LDP X1, X2, [SP], #16
100 LDP X8, X0, [SP], #16
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-ldst-subsuperReg-no-ldp.mir12 # CHECK-NOT: LDP
26 # CHECK-NOT: LDP
H A Daarch64-ldst-modified-baseReg.mir15 # CHECK-NOT: LDP
53 # CHECK-NOT: LDP
72 # CHECK-NOT: LDP
H A Dtailcall-implicit-sret.ll2 ; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks.
H A Dtailcall-explicit-sret.ll2 ; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks.
H A Dfold-global-offsets.ll63 ; FIXME: GlobalISel misses the opportunity to form a LDP here.
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-diags.s182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
218 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopDataPrefetch.cpp182 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in run() local
183 bool Changed = LDP.run(); in run()
209 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in runOnFunction() local
210 return LDP.run(); in runOnFunction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td62 // LDP,LDPSW,LDNP,LDXP,LDAXP
H A DAArch64FalkorHWPFFix.cpp133 FalkorMarkStridedAccesses LDP(LI, SE); in runOnFunction() local
134 return LDP.run(); in runOnFunction()
H A DAArch64SchedTSV110.td431 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instregex "^LDP(W|X)i$")>;
432 def : InstRW<[TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi, WriteAdr],(instregex "^LDP(W|X)(post|pre)$")>;
507 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi, WriteAdr], (instregex "^LDP[DQS](post|pre)")>;
H A DAArch64SchedFalkorDetails.td1106 (instregex "LDP(D|S)i$")>;
1108 (instregex "LDP(D|S)(pre|post)$")>;
1170 (instregex "^LDP(W|X)i$")>;
1172 (instregex "^LDP(W|X)(post|pre)$")>;
H A DAArch64SchedA55.td266 def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)i")>;
270 def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;
H A DAArch64SchedExynosM4.td617 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
698 WriteAdr], (instregex "^LDP[SD]post")>;
704 WriteAdr], (instregex "^LDP[SD]pre")>;
H A DAArch64SchedExynosM3.td520 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
583 WriteAdr], (instregex "^LDP[DS](post|pre)")>;
H A DAArch64SchedAmpere1.td672 } // The second register of a load-pair: LDP,LDPSW,LDNP,LDXP,LDAXP
958 (instregex "(LDNP|LDP|LDPSW)(X|W)")>;
H A DAArch64SchedExynosM5.td674 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
754 WriteAdr], (instregex "^LDP[SD](post|pre)")>;
H A DAArch64SchedThunderX3T110.td324 // Load vector pair, immed offset, Q-form [LDP/LDNP].
334 // Load vector pair, immed offset, S/D-form [LDP/LDNP].
872 // LDP only breaks into *one* LS micro-op. Thus
H A DAArch64ISelLowering.h452 LDP, enumerator
H A DAArch64SchedCyclone.td271 // LDP high register write is fused with the load, but a nop micro-op remains.
H A DAArch64SchedKryoDetails.td1420 (instregex "LDP(D|S)(post|pre)")>;
1432 (instregex "LDP(W|X)(post|pre)")>;
H A DAArch64SchedThunderX2T99.td613 // LDP only breaks into *one* LS micro-op. Thus
H A DAArch64SchedNeoverseN2.td865 (instregex "^LDP[SD](pre|post)$")>;
H A DAArch64SchedA64FX.td1002 // LDP only breaks into *one* LS micro-op. Thus
H A DAArch64ISelLowering.cpp2311 MAKE_CASE(AArch64ISD::LDP) in getTargetNodeName()
20303 AArch64ISD::LDP, SDLoc(N), in ReplaceNodeResults()

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