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/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst52 ``LDR`` and ``LD1``
66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering.
76 …2. The content of a vector register is the same *as if* it had been loaded with an ``LD1`` instruc…
78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…
133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we…
143 | | ``LDR`` layout | ``LD1`` layout |
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvcombine.ll7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
42 ; CHECK-LE: vmov r2, r3, [[LD1]]
57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
59 ; CHECK-LE: vmov r2, r3, [[LD1]]
73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
75 ; CHECK-LE: vmov r2, r3, [[LD1]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dproxy-reg-erasure-ptx.ll79 ; PTX-DAG: ld.param.v2.b64 {[[LD0:%rd[0-9]+]], [[LD1:%rd[0-9]+]]}, [retval0+0];
83 ; PTX-WITHOUT-DAG: mov.b64 [[PROXY1:%rd[0-9]+]], [[LD1]];
85 ; PTX-WITH-DAG: st.param.v2.b64 [func_retval0+0], {[[LD0]], [[LD1]]};
140 …; PTX-DAG: ld.param.v4.b32 {[[LD0:%r[0-9]+]], [[LD1:%r[0-9]+]], [[LD2:%r[0-9]+]], [[LD3:%r[0-9]+]]…
144 ; PTX-WITHOUT-DAG: mov.b32 [[PROXY1:%r[0-9]+]], [[LD1]];
148 ; PTX-WITH-DAG: st.param.v4.b32 [func_retval0+0], {[[LD0]], [[LD1]], [[LD2]], [[LD3]]};
173 ; PTX-DAG: ld.param.v2.f64 {[[LD0:%fd[0-9]+]], [[LD1:%fd[0-9]+]]}, [retval0+0];
177 ; PTX-WITHOUT-DAG: mov.f64 [[PROXY1:%fd[0-9]+]], [[LD1]];
179 ; PTX-WITH-DAG: st.param.v2.f64 [func_retval0+0], {[[LD0]], [[LD1]]};
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dmultiple-uses-load-bitcast-select.ll8 ; CHECK-NEXT: [[LD1:%.*]] = load double, double* [[Y1]], align 8
10 ; CHECK-NEXT: [[TMP10:%.*]] = fcmp olt double [[LD1]], [[LD2]]
11 ; CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP10]], double [[LD1]], double [[LD2]]
H A Dload-bitcast-select.ll88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmerge-store-partially-alias-loads.ll22 ; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<(load (s8) from %ir.tmp12)> [[ENTRYTOKEN]], [[ADDPTR]],…
24 ; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<(store (s8) into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], t{{…
25 ; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dtsc-s116.ll24 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[GEP1]], align 4
33 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[LD1]], i32 0
34 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[LD1]], i32 1
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dunal-altivec.ll37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
H A Dbotheightreduce.mir32 ; CHECK: [[LD1:%[0-9]+]]:g8rc = LD 4, [[ADDI8_]] :: (load (s64))
42 ; CHECK: [[MULLD3:%[0-9]+]]:g8rc = MULLD [[MULLD2]], [[LD1]]
H A Daix-vector-vararg-fixed-caller.ll63 ; 64BIT: [[LD1:%[0-9]+]]:g8rc = LD 96, $x1 :: (load (s64))
78 ; 64BIT: $x9 = COPY [[LD1]]
H A Daix-vector-vararg-caller.ll110 ; 64BIT: [[LD1:%[0-9]+]]:g8rc = LD 96, $x1 :: (load (s64))
121 ; 64BIT: $x9 = COPY [[LD1]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-gather-scatter-dag-combine.ll3 ; Verify that DAG combine rules for LD1 + sext/zext don't apply when the
4 ; result of LD1 has multiple uses
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dctpop.ll32 ; SSE42-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64,…
34 ; SSE42-NEXT: [[CTPOP1:%.*]] = call i64 @llvm.ctpop.i64(i64 [[LD1]])
41 ; AVX1-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64, …
43 ; AVX1-NEXT: [[CTPOP1:%.*]] = call i64 @llvm.ctpop.i64(i64 [[LD1]])
79 ; SSE42-NEXT: [[CTPOP1:%.*]] = call i64 @llvm.ctpop.i64(i64 [[LD1]])
90 ; AVX1-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64, …
94 ; AVX1-NEXT: [[CTPOP1:%.*]] = call i64 @llvm.ctpop.i64(i64 [[LD1]])
137 ; SSE42-NEXT: [[CTPOP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[LD1]])
152 ; AVX1-NEXT: [[CTPOP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[LD1]])
202 ; SSE42-NEXT: [[CTPOP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[LD1]])
[all …]
H A Dfround.ll33 ; SSE2-NEXT: [[CEIL1:%.*]] = call double @llvm.ceil.f64(double [[LD1]])
66 ; SSE2-NEXT: [[CEIL1:%.*]] = call double @llvm.ceil.f64(double [[LD1]])
116 ; SSE2-NEXT: [[CEIL1:%.*]] = call double @llvm.ceil.f64(double [[LD1]])
546 ; SSE2-NEXT: [[RINT1:%.*]] = call double @llvm.rint.f64(double [[LD1]])
579 ; SSE2-NEXT: [[RINT1:%.*]] = call double @llvm.rint.f64(double [[LD1]])
890 ; SSE2-NEXT: [[CEIL1:%.*]] = call float @llvm.ceil.f32(float [[LD1]])
937 ; SSE2-NEXT: [[CEIL1:%.*]] = call float @llvm.ceil.f32(float [[LD1]])
1015 ; SSE2-NEXT: [[CEIL1:%.*]] = call float @llvm.ceil.f32(float [[LD1]])
1655 ; SSE2-NEXT: [[RINT1:%.*]] = call float @llvm.rint.f32(float [[LD1]])
1702 ; SSE2-NEXT: [[RINT1:%.*]] = call float @llvm.rint.f32(float [[LD1]])
[all …]
H A Dcttz.ll30 ; CHECK-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64,…
32 ; CHECK-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 false)
53 ; SSE-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 false)
68 ; AVX1-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 false)
105 ; SSE2-NEXT: [[CTTZ1:%.*]] = call i32 @llvm.cttz.i32(i32 [[LD1]], i1 false)
152 ; SSE2-NEXT: [[CTTZ1:%.*]] = call i32 @llvm.cttz.i32(i32 [[LD1]], i1 false)
494 ; CHECK-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 true)
515 ; SSE-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 true)
530 ; AVX1-NEXT: [[CTTZ1:%.*]] = call i64 @llvm.cttz.i64(i64 [[LD1]], i1 true)
567 ; SSE2-NEXT: [[CTTZ1:%.*]] = call i32 @llvm.cttz.i32(i32 [[LD1]], i1 true)
[all …]
H A Dctlz.ll30 ; CHECK-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64,…
32 ; CHECK-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 false)
53 ; SSE-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 false)
68 ; AVX1-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 false)
105 ; SSE2-NEXT: [[CTLZ1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[LD1]], i1 false)
152 ; SSE2-NEXT: [[CTLZ1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[LD1]], i1 false)
494 ; CHECK-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 true)
515 ; SSE-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 true)
530 ; AVX1-NEXT: [[CTLZ1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[LD1]], i1 true)
567 ; SSE2-NEXT: [[CTLZ1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[LD1]], i1 true)
[all …]
H A Dbswap.ll22 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64, i…
24 ; SSE-NEXT: [[BSWAP1:%.*]] = call i64 @llvm.bswap.i64(i64 [[LD1]])
47 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64, i…
51 ; SSE-NEXT: [[BSWAP1:%.*]] = call i64 @llvm.bswap.i64(i64 [[LD1]])
H A Dsitofp.ll26 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
28 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
37 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
66 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
70 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
85 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
124 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
132 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
159 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
542 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
[all …]
H A Dsitofp-inseltpoison.ll26 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
28 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
37 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
66 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
70 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
85 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
124 ; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i…
132 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
159 ; AVX256NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
542 ; SSE-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
[all …]
H A Dbad-reduction.ll197 ; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[G1]], align 1
205 ; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64
283 ; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[G1]], align 1
291 ; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcall-translator-ios.ll62 ; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
70 ; CHECK: G_STORE [[LD1]](s64), [[ADDR]](p0) :: (store (s64) into stack, align 1)
H A Dcall-translator.ll85 ; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr)
93 ; CHECK: $d0 = COPY [[LD1]](s64)
104 ; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.addr)
115 ; CHECK: $x0 = COPY [[LD1]](s64)
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Daddr-space-struct-arg.cl166 // AMDGCN: %[[LD1:.*]] = load <2 x i32>, <2 x i32> addrspace(5)*
167 // AMDGCN: call void @FuncTwoMember(<2 x i32> %[[LD0]], <2 x i32> %[[LD1]])
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dcgscc-cycle.ll160 ; CHECK-NEXT: %[[LD1:.*]] = load i64, i64* @a
161 ; CHECK-NEXT: %[[ADD1:.*]] = add nsw i64 %[[LD1]], 1
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dtail-pred-basic.ll11 ; CHECK: [[LD1:%[^ ]+]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* {{.*}}, i3…
59 ; CHECK: [[LD1:%[^ ]+]] = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* {{.*}}, i3…
106 ; CHECK: [[LD1:%[^ ]+]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i3…
154 ; CHECK: [[LD1:%[^ ]+]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i3…
206 ; CHECK: [[LD1:%[^ ]+]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i3…
262 ; CHECK: [[LD1:%[^ ]+]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i3…

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