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/llvm-project-15.0.7/lld/test/ELF/
H A Dppc64-tls-pcrel-ld.s8 # RUN: llvm-readelf -s %t-ld.so | FileCheck %s --check-prefix=LD-SYM
18 ## LD - Local Dynamic with no relaxation possible
24 # LD-SYM: Symbol table '.symtab' contains 11 entries:
28 # LD-GOT: section '.got':
29 # LD-GOT-NEXT: 0x01004160 60c10001 00000000 00000000 00000000
30 # LD-GOT-NEXT: 0x01004170 00000000 00000000
50 # LD-LABEL: <LDAddr>:
51 # LD: paddi 3, 0, 12644, 1
52 # LD-NEXT: bl 0x1001020
53 # LD-NEXT: paddi 3, 3, -32768, 0
[all …]
H A Dppc32-tls-ld.s13 # LD-REL: .rela.dyn {
15 # LD-REL-NEXT: }
18 # LD: addi 3, 30, 12
19 # LD-NEXT: bl 0x101f8
22 # LD-NEXT: addis 9, 3, 1
23 # LD-NEXT: addis 10, 3, 2
24 # LD-NEXT: addi 9, 9, -32764
27 # LD-NEXT: addi 9, 3, -32764
32 # LD-NEXT: addi 3, 9, 12
33 # LD-NEXT: bl 0x101f8
[all …]
H A Dx86-64-tlsdesc-ld.s5 # RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=LD-REL %s
6 # RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=LD %s
12 ## Check _TLS_MODULE_BASE_ used by LD produces a dynamic relocation with a value of 0.
13 # LD-REL: .rela.dyn {
14 # LD-REL-NEXT: 0x2318 R_X86_64_TLSDESC - 0x0
15 # LD-REL-NEXT: }
19 # LD: leaq 4273(%rip), %rax
20 # LD-NEXT: 1267: callq *(%rax)
21 # LD-NEXT: movl %fs:8(%rax), %edx
22 # LD-NEXT: addl %fs:12(%rax), %edx
[all …]
H A Di386-tlsdesc-ld.s5 # RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=LD-REL %s
6 # RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=LD %s
12 ## Check _TLS_MODULE_BASE_ used by LD produces a dynamic relocation with a value of 0.
13 # LD-REL: .rel.dyn {
14 # LD-REL-NEXT: R_386_TLS_DESC -
15 # LD-REL-NEXT: }
19 # LD: leal -8(%ebx), %eax
20 # LD-NEXT: calll *(%eax)
21 # LD-NEXT: leal 8(%eax), %ecx
22 # LD-NEXT: leal 12(%eax), %edx
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins.c215 res = __builtin_isinf(LD); in test_float_builtins()
297 resld = __builtin_fmodl(LD,LD); in test_float_builtin_ops()
302 resld = __builtin_fabsl(LD); in test_float_builtin_ops()
320 resld = __builtin_fminl(LD, LD); in test_float_builtin_ops()
329 resld = __builtin_fmaxl(LD, LD); in test_float_builtin_ops()
338 resld = __builtin_fabsl(LD); in test_float_builtin_ops()
347 resld = __builtin_copysignl(LD, LD); in test_float_builtin_ops()
357 resld = __builtin_ceill(LD); in test_float_builtin_ops()
366 resld = __builtin_floorl(LD); in test_float_builtin_ops()
375 resld = __builtin_sqrtl(LD); in test_float_builtin_ops()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dproxy-reg-erasure-ptx.ll15 ; PTX-DAG: ld.param.b32 [[LD:%r[0-9]+]], [retval0+0];
18 ; PTX-WITHOUT-DAG: mov.b32 [[PROXY:%r[0-9]+]], [[LD]];
20 ; PTX-WITH-DAG: and.b32 [[RES:%r[0-9]+]], [[LD]], 1;
32 ; PTX-DAG: ld.param.b32 [[LD:%r[0-9]+]], [retval0+0];
35 ; PTX-WITHOUT-DAG: mov.b32 [[PROXY:%r[0-9]+]], [[LD]];
49 ; PTX-DAG: ld.param.b32 [[LD:%r[0-9]+]], [retval0+0];
52 ; PTX-WITHOUT-DAG: mov.b32 [[PROXY:%r[0-9]+]], [[LD]];
64 ; PTX-DAG: ld.param.b64 [[LD:%rd[0-9]+]], [retval0+0];
95 ; PTX-DAG: ld.param.b16 [[LD:%h[0-9]+]], [retval0+0];
98 ; PTX-WITHOUT-DAG: mov.b16 [[PROXY:%h[0-9]+]], [[LD]];
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dextract.ll17 %LD = load <2 x double>, <2 x double>* undef
18 %V0 = extractelement <2 x double> %LD, i32 0
19 %V1 = extractelement <2 x double> %LD, i32 1
41 %LD = load <2 x double>, <2 x double>* undef
42 %V0 = extractelement <2 x double> %LD, i32 0
43 %V1 = extractelement <2 x double> %LD, i32 1
57 ; CHECK-NEXT: [[V0:%.*]] = extractelement <4 x double> [[LD]], i32 0
58 ; CHECK-NEXT: [[V1:%.*]] = extractelement <4 x double> [[LD]], i32 1
68 %LD = load <4 x double>, <4 x double>* undef
69 %V0 = extractelement <4 x double> %LD, i32 0 ; <--- invalid size.
[all …]
H A Dremark_extract_broadcast.ll8 ; CHECK-NEXT: [[LD:%.*]] = load <8 x i16>, <8 x i16>* undef, align 16
13 ; CHECK-NEXT: [[TMP0:%.*]] = add <8 x i16> [[LD]], [[SHUFFLE]]
28 %LD = load <8 x i16>, <8 x i16>* undef
29 %V0 = extractelement <8 x i16> %LD, i32 0
33 %V1 = extractelement <8 x i16> %LD, i32 1
34 %V2 = extractelement <8 x i16> %LD, i32 2
35 %V3 = extractelement <8 x i16> %LD, i32 3
36 %V4 = extractelement <8 x i16> %LD, i32 4
37 %V5 = extractelement <8 x i16> %LD, i32 5
38 %V6 = extractelement <8 x i16> %LD, i32 6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfold-frame-offset-using-rr.mir24 $x6 = LD 4, killed $x4
40 $x6 = LD 4, killed $x3
58 $x6 = LD 4, killed $x3
76 $x6 = LD 4, killed $x3
94 $x6 = LD 4, killed $x4
110 $x6 = LD 4, $x4
111 ; CHECK: $x6 = LD 4, $x4
127 $x3 = LD 100, $x6
131 $x6 = LD 4, killed $x4
147 $x5 = LD 100, $x6
[all …]
H A Dldst-16-byte.mir130 ; CHECK: $x8 = LD -224, $x1
131 ; CHECK: $x9 = LD -216, $x1
133 ; CHECK: $x8 = LD -208, $x1
134 ; CHECK: $x9 = LD -200, $x1
136 ; CHECK: $x8 = LD -192, $x1
137 ; CHECK: $x9 = LD -184, $x1
139 ; CHECK: $x8 = LD -176, $x1
140 ; CHECK: $x9 = LD -168, $x1
143 ; CHECK: $x8 = LD -160, $x1
144 ; CHECK: $x9 = LD -152, $x1
[all …]
H A Dbotheightreduce.mir4 # Check that machine-scheduler's BotHeightReduce heuristic puts the LD 8 in
29 ; CHECK: [[LD:%[0-9]+]]:g8rc = LD 0, [[ADDI8_]] :: (load (s64))
32 ; CHECK: [[LD1:%[0-9]+]]:g8rc = LD 4, [[ADDI8_]] :: (load (s64))
36 ; CHECK: [[LD2:%[0-9]+]]:g8rc = LD 8, [[ADDI8_]] :: (load (s64))
37 ; CHECK: [[MULLD:%[0-9]+]]:g8rc = MULLD [[LDX]], [[LD]]
70 %13:g8rc = LD 0, %2 :: (load (s64))
73 %17:g8rc = LD 4, %2 :: (load (s64))
77 %21:g8rc = LD 8, %2 :: (load (s64))
H A Dsink-down-more-instructions-regpressure-high.mir464 …; CHECK: [[LD:%[0-9]+]]:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.28 :: (load (s64) from %fixed-st…
635 %59:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.1 :: (load (s64) from %fixed-stack.1)
637 %57:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.3 :: (load (s64) from %fixed-stack.3)
639 %55:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.5 :: (load (s64) from %fixed-stack.5)
641 %53:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7)
643 %51:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.9 :: (load (s64) from %fixed-stack.9)
645 %49:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.11 :: (load (s64) from %fixed-stack.11)
647 %47:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.13 :: (load (s64) from %fixed-stack.13)
649 %45:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.15 :: (load (s64) from %fixed-stack.15)
651 %43:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.17 :: (load (s64) from %fixed-stack.17)
[all …]
H A Dtopdepthreduce-postra.mir10 ; CHECK: renamable $x5 = LD 0, killed renamable $x5 :: (load (s64))
11 ; CHECK: renamable $x4 = LD 0, killed renamable $x4 :: (load (s64))
14 renamable $x5 = LD 0, killed renamable $x5 :: (load (s64))
16 renamable $x4 = LD 0, killed renamable $x4 :: (load (s64))
H A Dmacro-fusion.ll11 ; CHECK-P8: Macro fuse: SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]]) / ADDIStocHA8 - LD
13 ; CHECK-P8: SU([[SU1]]): %{{[0-9]+}}:g8rc = LD target-flags(ppc-toc-lo) @m, %[[REG3]]
16 ; CHECK-P8: Macro fuse: SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]]) / ADDIStocHA8 - LD
18 ; CHECK-P8: SU([[SU1]]): renamable $x[[REG3]] = LD target-flags(ppc-toc-lo) @m, renamable $x[[REG…
H A DPR33671.ll13 ; CHECK: lxv [[LD:[0-9]+]], 16(3)
14 ; CHECK: stxv [[LD]], 16(4)
29 ; CHECK: lxvx [[LD:[0-9]+]], 3, [[REG]]
31 ; CHECK: stxvx [[LD]], 4, [[REG2]]
H A Daix64-cc-byval.ll129 ; CHECK-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64))
130 ; CHECK-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load (s64))
131 ; CHECK-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load (s64))
132 ; CHECK-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load (s64))
133 ; CHECK-DAG: renamable $x7 = LD 32, renamable $x[[REGADDR]] :: (load (s64))
134 ; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load (s64))
135 ; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load (s64))
136 ; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load (s64))
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Demergency-spill.mir147 $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
152 $at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
153 $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
154 $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
155 $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
156 $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
157 $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
158 $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
159 $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
160 $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
[all …]
/llvm-project-15.0.7/polly/lib/External/isl/imath/contrib/
H A DMakefile.msvc19 LD=link.exe
62 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
67 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
70 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
73 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
76 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
79 $(LD) $(LDFLAGS) -out:$@ $** $(LIBS)
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp297 static bool isValidIndexedLoad(const LoadSDNode *LD) { in isValidIndexedLoad() argument
298 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
302 EVT VT = LD->getMemoryVT(); in isValidIndexedLoad()
323 LoadSDNode *LD = cast<LoadSDNode>(N); in tryIndexedLoad() local
324 if (!isValidIndexedLoad(LD)) in tryIndexedLoad()
327 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedLoad()
343 LD->getBasePtr(), LD->getChain())); in tryIndexedLoad()
352 LoadSDNode *LD = cast<LoadSDNode>(N1); in tryIndexedBinOp() local
353 if (!isValidIndexedLoad(LD)) in tryIndexedBinOp()
356 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedBinOp()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-codegen-prepare-extload.ll9 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
29 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
55 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
87 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
119 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
149 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
185 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
220 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
357 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
641 ; OPT: %[[LD:.*]] = load i16, i16* %P
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcodegen-prepare-extload.ll15 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
35 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
39 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
61 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
64 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
93 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
125 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
155 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
191 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
226 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsetcc-limit-load-shrink.ll5 ; GCN: s_load_dword [[LD:s[0-9]+]],
6 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
19 ; GCN: s_load_dword [[LD:s[0-9]+]],
20 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
33 ; GCN: s_load_dword [[LD:s[0-9]+]],
34 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
47 ; GCN: s_load_dword [[LD:s[0-9]+]],
48 ; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp122 const LoadSDNode *LD = cast<LoadSDNode>(N); in selectIndexedLoad() local
123 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
124 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad()
161 LD->getBasePtr(), LD->getChain()); in selectIndexedLoad()
171 if (LD->getExtensionType() != ISD::NON_EXTLOAD || in selectIndexedProgMemLoad()
172 LD->getAddressingMode() != ISD::POST_INC) in selectIndexedProgMemLoad()
353 const LoadSDNode *LD = cast<LoadSDNode>(N); in select() local
354 if (!AVR::isProgramMemoryAccess(LD)) { in select()
368 MVT VT = LD->getMemoryVT().getSimpleVT(); in select()
369 SDValue Chain = LD->getChain(); in select()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dmake-compressible-rv64.mir188 ; CHECK-NEXT: dead renamable $x10 = LD $x11, 0 :: (volatile load (s64) from %ir.p)
189 ; CHECK-NEXT: dead renamable $x10 = LD $x11, 0 :: (volatile load (s64) from %ir.p)
192 dead renamable $x10 = LD renamable $x16, 0 :: (volatile load (s64) from %ir.p)
193 dead renamable $x10 = LD renamable $x16, 0 :: (volatile load (s64) from %ir.p)
240 ; CHECK-NEXT: dead renamable $x11 = LD $x12, 32 :: (volatile load (s64) from %ir.0)
241 ; CHECK-NEXT: dead renamable $x11 = LD $x12, 40 :: (volatile load (s64) from %ir.1)
242 ; CHECK-NEXT: dead renamable $x11 = LD $x12, 48 :: (volatile load (s64) from %ir.2)
245 dead renamable $x11 = LD renamable $x10, 800 :: (volatile load (s64) from %ir.0)
246 dead renamable $x11 = LD renamable $x10, 808 :: (volatile load (s64) from %ir.1)
247 dead renamable $x11 = LD renamable $x10, 816 :: (volatile load (s64) from %ir.2)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir141 ; CHECK-NEXT: $x5 = LD $x2, 0 :: (load (s64) from %stack.16)
143 ; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.15)
159 ; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
160 ; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
161 ; CHECK-NEXT: $x18 = LD $x2, 2008 :: (load (s64) from %stack.5)
162 ; CHECK-NEXT: $x19 = LD $x2, 2000 :: (load (s64) from %stack.6)
163 ; CHECK-NEXT: $x20 = LD $x2, 1992 :: (load (s64) from %stack.7)
164 ; CHECK-NEXT: $x21 = LD $x2, 1984 :: (load (s64) from %stack.8)
165 ; CHECK-NEXT: $x22 = LD $x2, 1976 :: (load (s64) from %stack.9)
166 ; CHECK-NEXT: $x23 = LD $x2, 1968 :: (load (s64) from %stack.10)
[all …]

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