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Searched refs:IsRet (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h611 bool IsFixed, bool IsRet, Type *OrigTy,
616 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
620 bool IsRet, CallLoweringInfo *CLI,
H A DRISCVISelLowering.cpp10348 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, in CC_RISCV() argument
10356 if (!LocVT.isVector() && IsRet && ValNo > 1) in CC_RISCV()
10499 if (IsRet) in CC_RISCV()
10573 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
10587 if (IsRet) in analyzeInputArgs()
10594 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this, in analyzeInputArgs()
10605 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
10620 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, in analyzeOutputArgs()
10777 bool IsFixed, bool IsRet, Type *OrigTy, in CC_RISCV_FastCC() argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td2693 bit IsRet = isRet;
2869 let ColFields = ["IsRet"];