Searched refs:IsPre (Results 1 – 4 of 4) sorted by relevance
1388 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1398 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1401 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1403 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1405 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1418 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1438 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost; in tryIndexedLoad()1440 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost; in tryIndexedLoad()1442 Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost; in tryIndexedLoad()1444 Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost; in tryIndexedLoad()[all …]
58 bool IsPre; member
1040 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()1042 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()1085 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
3473 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument