Searched refs:IsFSHR (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1303 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift() local
1322 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); in PromoteIntRes_FunnelShift()
1323 if (!IsFSHR) in PromoteIntRes_FunnelShift()
1334 if (IsFSHR) in PromoteIntRes_FunnelShift()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30399 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift() local
30406 if (IsFSHR) in LowerFunnelShift()
30412 return getAVX512Node(IsFSHR ? X86ISD::VSHRD : X86ISD::VSHLD, DL, VT, in LowerFunnelShift()
30415 return getAVX512Node(IsFSHR ? X86ISD::VSHRDV : X86ISD::VSHLDV, DL, VT, in LowerFunnelShift()
30436 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL; in LowerFunnelShift()
30466 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, !IsFSHR); in LowerFunnelShift()
30490 if (!IsFSHR) in LowerFunnelShift()
30497 if (((IsCst || !Subtarget.hasAVX512()) && !IsFSHR && EltSizeInBits <= 16) || in LowerFunnelShift()
30506 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, !IsFSHR); in LowerFunnelShift()
30531 if (IsFSHR) { in LowerFunnelShift()
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