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Searched refs:IntRegs (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td608 def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
614 def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
630 def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
696 def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1070 def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1074 def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1172 def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1198 def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1202 def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1204 def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
[all …]
H A DHexagonDepMappings.td11 def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
12 def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
13 …fAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
15 …rtAlias : InstAlias<"if ($Pu4) $Rd32 = $Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
19 def A2_zxtbAlias : InstAlias<"$Rd32 = zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
34 def L2_loadrb_zomapAlias : InstAlias<"$Rd32 = memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$R…
36 def L2_loadrh_zomapAlias : InstAlias<"$Rd32 = memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$R…
37 def L2_loadri_zomapAlias : InstAlias<"$Rd32 = memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$R…
38 def L2_loadrub_zomapAlias : InstAlias<"$Rd32 = memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs…
39 def L2_loadruh_zomapAlias : InstAlias<"$Rd32 = memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs…
[all …]
H A DHexagonIntrinsics.td23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
38 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
40 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
44 (M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt)>;
46 (M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt)>;
62 (A2_and IntRegs:$Rs, IntRegs:$Rt)>;
66 (A2_or IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
H A DHexagonDepInstrInfo.td45 (ins IntRegs:$Rs32, IntRegs:$Rt32),
61 (ins IntRegs:$Rt32, IntRegs:$Rs32),
73 (ins IntRegs:$Rt32, IntRegs:$Rs32),
85 (ins IntRegs:$Rt32, IntRegs:$Rs32),
97 (ins IntRegs:$Rt32, IntRegs:$Rs32),
109 (ins IntRegs:$Rt32, IntRegs:$Rs32),
4673 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4687 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4715 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4729 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
47 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
48 (MI HvxWR:$src1, IntRegs:$src2)>;
50 (MI HvxWR:$src1, IntRegs:$src2)>;
71 (MI HvxQR:$src1, IntRegs:$src2)>;
73 (MI HvxQR:$src1, IntRegs:$src2)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
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H A DHexagonIntrinsicsV60.td66 (V6_vS32b_ai IntRegs:$addr, 0,
70 def : Pat <(v64i1 (load (i32 IntRegs:$addr))),
75 (V6_vS32b_ai IntRegs:$addr, 0,
79 def : Pat <(v128i1 (load (i32 IntRegs:$addr))),
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
87 (MI IntRegs:$src1)>;
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
[all …]
H A DHexagonPatternsV65.td13 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
23 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
33 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
47 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
48 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
58 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
69 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
[all …]
H A DHexagonPseudo.td13 def I32 : PatLeaf<(i32 IntRegs:$R)>;
15 def F32 : PatLeaf<(f32 IntRegs:$R)>;
25 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
44 : InstHexagon<(outs IntRegs:$dst),
282 def PS_fi : Pseudo<(outs IntRegs:$Rd),
285 def PS_fia : Pseudo<(outs IntRegs:$Rd),
286 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
554 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs),
559 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs),
577 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
[all …]
H A DHexagonPatterns.td749 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
753 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
924 (InstA IntRegs:$Rs, IntRegs:$Rt)>;
927 (InstB IntRegs:$Rs, IntRegs:$Rt)>;
1709 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
1789 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1791 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1825 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1850 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
1855 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
H A DHexagonIntrinsicsV5.td177 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonRegisterInfo.td533 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
47 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
144 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
154 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
165 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
199 (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
386 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
398 def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
414 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
418 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
[all …]
H A DSparcInstrInfo.td377 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
499 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
520 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
542 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
729 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
739 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
748 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1641 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1652 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1663 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
[all …]
H A DSparcInstr64Bit.td22 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
207 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
216 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
243 (outs IntRegs:$dst),
324 def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
325 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
329 def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
330 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
393 (ins I64Regs:$rs1, IntRegs:$rs2),
[all …]
H A DSparcRegisterInfo.td329 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
335 // Should be in the same order as IntRegs.
344 // to be a sub-class of IntRegs. That works out because requiring a 64-bit
346 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
H A DSparcInstrFormats.td229 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
/llvm-project-15.0.7/llvm/docs/
H A DHowToUseInstrMappings.rst121 def ADD : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
123 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
126 def ADD_Pt : ALU32_rr<(outs IntRegs:$dst),
127 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
131 def ADD_Pf : ALU32_rr<(outs IntRegs:$dst),
132 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
142 def ADD : PredRel, ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
144 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
150 def ADD_Pt : PredRel, ALU32_rr<(outs IntRegs:$dst),
151 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
[all …]
H A DWritingAnLLVMBackend.rst576 // IntRegs Register Class...
577 static const unsigned IntRegs[] = {
596 // IntRegs Sub-register Classes...
601 // IntRegs Super-register Classes..
606 // IntRegs Register Class sub-classes...
618 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
761 target description file (``IntRegs``).
776 let MIOperandInfo = (ops IntRegs, IntRegs);
808 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
812 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
[all …]
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCWin64EH.cpp716 IntRegs, in tryARM64PackedUnwind() enumerator
744 Location = IntRegs; in tryARM64PackedUnwind()
1537 IntRegs = -1; in parseRegMask()
1562 IntRegs = N - 1; in parseRegMask()
1618 IntRegs--; in tryARMPackedUnwind()
1665 if (IntRegs >= 0) in tryARMPackedUnwind()
1685 if (IntRegs + 4 == 10) { in tryARMPackedUnwind()
1688 IntRegs++; in tryARMPackedUnwind()
1818 if (IntRegs != 6) in tryARMPackedUnwind()
1940 if (IntRegs >= 0) { in tryARMPackedUnwind()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp143 static const MCPhysReg IntRegs[32] = { variable
1314 RegNo = IntRegs[intVal]; in matchRegisterName()
1321 RegNo = IntRegs[8 + intVal]; in matchRegisterName()
1327 RegNo = IntRegs[16 + intVal]; in matchRegisterName()
1333 RegNo = IntRegs[24 + intVal]; in matchRegisterName()
1357 RegNo = IntRegs[intVal]; in matchRegisterName()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dswp-intreglow8.ll7 ; from IntRegsLow8 to IntRegs, which is incorrect.
H A Dcirc_ldd_bug.ll10 ; %0 (CRRegs) = TFCR %0 (IntRegs)
12 ; %1 (CRRegs) = TFCR %1 (IntRegs)
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2870 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; in CC_MipsO32() local
2932 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2936 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2940 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2947 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2949 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2954 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32()
2965 State.AllocateReg(IntRegs); in CC_MipsO32()
2969 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()
2971 State.AllocateReg(IntRegs); in CC_MipsO32()
[all …]