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Searched refs:InstRef (Results 1 – 25 of 35) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h36 virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const = 0;
51 bool compare(const InstRef &Lhs, const InstRef &Rhs) const override { in compare()
111 std::vector<InstRef> WaitSet;
112 std::vector<InstRef> PendingSet;
113 std::vector<InstRef> ReadySet;
114 std::vector<InstRef> IssuedSet;
138 InstRef &IR,
198 bool dispatch(InstRef &IR);
204 InstRef &IR,
207 SmallVectorImpl<InstRef> &Ready);
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H A DLSUnit.h49 InstRef CriticalMemoryInstruction;
75 const InstRef &getCriticalMemoryInstruction() const { in getCriticalMemoryInstruction()
135 void onInstructionIssued(const InstRef &IR) { in onInstructionIssued()
163 void onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
264 virtual unsigned dispatch(const InstRef &IR) = 0;
276 bool isReady(const InstRef &IR) const { in isReady()
284 bool isPending(const InstRef &IR) const { in isPending()
292 bool isWaiting(const InstRef &IR) const { in isWaiting()
298 bool hasDependentUsers(const InstRef &IR) const { in hasDependentUsers()
326 virtual void onInstructionRetired(const InstRef &IR);
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H A DRetireControlUnit.h52 InstRef IR;
91 unsigned dispatch(const InstRef &IS);
/llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h37 InstRef IR;
46 InstRef &getInstruction() { return IR; } in getInstruction()
62 SmallVector<InstRef, 4> IssuedInst;
70 InstRef CarriedOver;
88 bool canExecute(const InstRef &IR);
91 Error tryIssue(InstRef &IR);
103 void notifyInstructionIssued(const InstRef &IR,
108 void notifyInstructionRetired(const InstRef &IR,
112 void retireInstruction(InstRef &IR);
119 bool isAvailable(const InstRef &) const override;
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H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
75 void notifyInstructionIssued(const InstRef &IR,
77 void notifyInstructionExecuted(const InstRef &IR) const;
78 void notifyInstructionPending(const InstRef &IR) const;
79 void notifyInstructionReady(const InstRef &IR) const;
83 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DDispatchStage.h53 InstRef CarriedOver;
58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
H A DStage.h25 class InstRef; variable
42 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable()
58 virtual Error execute(InstRef &IR) = 0;
65 bool checkNextStage(const InstRef &IR) const { in checkNextStage()
73 Error moveToTheNextStage(InstRef &IR) { in moveToTheNextStage()
H A DMicroOpQueueStage.h27 SmallVector<InstRef, 8> Buffer;
54 unsigned getNormalizedOpcodes(const InstRef &IR) const { in getNormalizedOpcodes()
67 bool isAvailable(const InstRef &IR) const override { in isAvailable()
80 Error execute(InstRef &IR) override;
H A DEntryStage.h27 InstRef CurrentInstruction;
41 bool isAvailable(const InstRef &IR) const override;
43 Error execute(InstRef &IR) override;
H A DRetireStage.h44 Error execute(InstRef &IR) override;
45 void notifyInstructionRetired(const InstRef &IR) const;
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp55 SmallVector<InstRef, 4> Pending; in issueInstruction()
56 SmallVector<InstRef, 4> Ready; in issueInstruction()
72 for (const InstRef &I : Pending) in issueInstruction()
75 for (const InstRef &I : Ready) in issueInstruction()
81 InstRef IR = HWS.select(); in issueReadyInstructions()
96 SmallVector<InstRef, 4> Pending; in cycleStart()
97 SmallVector<InstRef, 4> Ready; in cycleStart()
106 for (InstRef &IR : Executed) { in cycleStart()
116 for (const InstRef &IR : Ready) in cycleStart()
131 SmallVector<InstRef, 8> Insts; in cycleEnd()
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H A DInOrderIssueStage.cpp60 bool InOrderIssueStage::isAvailable(const InstRef &IR) const { in isAvailable()
88 static unsigned findFirstWriteBackCycle(const InstRef &IR) { in findFirstWriteBackCycle()
105 const InstRef &IR) { in checkRegisterHazard()
115 bool InOrderIssueStage::canExecute(const InstRef &IR) { in canExecute()
198 llvm::Error InOrderIssueStage::execute(InstRef &IR) { in execute()
212 llvm::Error InOrderIssueStage::tryIssue(InstRef &IR) { in tryIssue()
286 InstRef &IR = *I; in updateIssuedInst()
332 CarriedOver = InstRef(); in updateCarriedOver()
336 void InOrderIssueStage::retireInstruction(InstRef &IR) { in retireInstruction()
354 const InstRef &IR = SI.getInstruction(); in notifyStallEvent()
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H A DDispatchStage.cpp38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, in notifyInstructionDispatched()
46 bool DispatchStage::checkPRF(const InstRef &IR) const { in checkPRF()
62 bool DispatchStage::checkRCU(const InstRef &IR) const { in checkRCU()
71 bool DispatchStage::canDispatch(const InstRef &IR) const { in canDispatch()
78 Error DispatchStage::dispatch(InstRef IR) { in dispatch()
150 CarriedOver = InstRef(); in cycleStart()
154 bool DispatchStage::isAvailable(const InstRef &IR) const { in isAvailable()
174 Error DispatchStage::execute(InstRef &IR) { in execute()
H A DEntryStage.cpp25 bool EntryStage::isAvailable(const InstRef & /* unused */) const { in isAvailable()
41 CurrentInstruction = InstRef(SR.first, Inst.get()); in getNextInstruction()
47 llvm::Error EntryStage::execute(InstRef & /*unused */) { in execute() argument
H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions()
46 Error MicroOpQueueStage::execute(InstRef &IR) { in execute()
H A DRetireStage.cpp49 llvm::Error RetireStage::execute(InstRef &IR) { in execute()
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const { in notifyInstructionRetired()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp71 InstRef &IR, in issueInstructionImpl()
100 InstRef &IR, in issueInstruction()
124 InstRef &IR = *I; in promoteToReadySet()
160 InstRef &IR = *I; in promoteToPendingSet()
192 InstRef Scheduler::select() { in select()
195 InstRef &IR = ReadySet[I]; in select()
209 return InstRef(); in select()
221 InstRef &IR = *I; in updateIssuedSet()
273 for (InstRef &IR : IssuedSet) in cycleEvent()
277 for (InstRef &IR : PendingSet) in cycleEvent()
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H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { in dispatch()
196 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const { in isAvailable()
205 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
214 void LSUnitBase::onInstructionRetired(const InstRef &IR) { in onInstructionRetired()
233 void LSUnit::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DHWEventListener.h52 HWInstructionEvent(unsigned type, const InstRef &Inst) in HWInstructionEvent()
59 const InstRef &IR;
67 HWInstructionIssuedEvent(const InstRef &IR, ArrayRef<ResourceUse> UR) in HWInstructionIssuedEvent()
75 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
96 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
122 HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {} in HWStallEvent()
128 const InstRef &IR;
146 HWPressureEvent(GenericReason reason, ArrayRef<InstRef> Insts,
154 ArrayRef<InstRef> AffectedInstructions;
174 virtual void onReservedBuffers(const InstRef &Inst, in onReservedBuffers()
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H A DInstruction.h720 class InstRef {
724 InstRef() : Data(std::make_pair(0, nullptr)) {} in InstRef() function
725 InstRef(unsigned Index, Instruction *I) : Data(std::make_pair(Index, I)) {} in InstRef() function
727 bool operator==(const InstRef &Other) const { return Data == Other.Data; }
728 bool operator!=(const InstRef &Other) const { return Data != Other.Data; }
729 bool operator<(const InstRef &Other) const {
749 inline raw_ostream &operator<<(raw_ostream &OS, const InstRef &IR) {
H A DCustomBehaviour.h89 virtual unsigned checkCustomHazard(ArrayRef<InstRef> IssuedInst,
90 const InstRef &IR);
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.h78 unsigned handleWaitCnt(ArrayRef<InstRef> IssuedInst, const InstRef &IR);
82 void computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, unsigned &Expcnt,
97 unsigned checkCustomHazard(ArrayRef<InstRef> IssuedInst,
98 const InstRef &IR) override;
H A DAMDGPUCustomBehaviour.cpp67 unsigned AMDGPUCustomBehaviour::checkCustomHazard(ArrayRef<InstRef> IssuedInst, in checkCustomHazard()
68 const InstRef &IR) { in checkCustomHazard()
101 unsigned AMDGPUCustomBehaviour::handleWaitCnt(ArrayRef<InstRef> IssuedInst, in handleWaitCnt()
102 const InstRef &IR) { in handleWaitCnt()
123 for (const InstRef &PrevIR : IssuedInst) { in handleWaitCnt()
173 void AMDGPUCustomBehaviour::computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, in computeWaitCnt()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DCustomBehaviour.cpp21 unsigned CustomBehaviour::checkCustomHazard(ArrayRef<InstRef> IssuedInst, in checkCustomHazard()
22 const InstRef &IR) { in checkCustomHazard()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.h82 void onReservedBuffers(const InstRef &IR,
87 void onReleasedBuffers(const InstRef &IR,

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