Searched refs:InsertReg (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 1235 const Register InsertReg = I.getOperand(2).getReg(); in selectInsert() local
1239 const LLT InsertRegTy = MRI.getType(InsertReg); in selectInsert()
1250 if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF)) in selectInsert()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4099 Register InsertReg = VecReg; in emitExtractVectorElt() local
4118 InsertReg = ScalarToVector->getOperand(0).getReg(); in emitExtractVectorElt()
4122 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx); in emitExtractVectorElt()
4265 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass); in selectUnmergeValues() local
4268 TII.get(TargetOpcode::INSERT_SUBREG), InsertReg) in selectUnmergeValues()
4277 InsertRegs.push_back(InsertReg); in selectUnmergeValues()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2834 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
2837 LLT InsertTy = B.getMRI()->getType(InsertReg); in buildBitFieldInsert()
2838 auto ZextVal = B.buildZExt(TargetTy, InsertReg); in buildBitFieldInsert()
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